Semiconductor Diodes, Rectifiers & Filter Circuits

1. Energy Band Structure in Crystalline Solids

In isolated atoms, electronic energy levels are discrete. When $N$ atoms assemble into a periodic crystal lattice, the overlapping atomic orbitals split by the Pauli exclusion principle into dense quasi-continuous energy bands separated by forbidden energy gaps (bandgaps $E_g$):

• Valence Band ($E_V$): The highest occupied energy band composed of valence electron states forming interatomic covalent bonds. At absolute zero ($T = 0\text{ K}$), the valence band in pure semiconductors is completely filled.
• Conduction Band ($E_C$): The lowest unoccupied band above the valence band. Electrons excited into this band are delocalized and free to accelerate under applied electric fields.
• Forbidden Energy Gap ($E_g = E_C - E_V$): No quantum electron states can exist in this interval. For insulators, $E_g > 3.0\text{ eV}$ (e.g., diamond $E_g \approx 5.4\text{ eV}$). For semiconductors, $E_g$ is moderate: Silicon has $E_g \approx 1.12\text{ eV}$, and Germanium has $E_g \approx 0.67\text{ eV}$ at $300\text{ K}$. In metals, the conduction and valence bands overlap ($E_g = 0$).

2. Direct vs. Indirect Bandgap Semiconductors

In a direct bandgap semiconductor (e.g., GaAs with $E_g = 1.42\text{ eV}$, InP), the minimum of the conduction band and maximum of the valence band align at the exact same crystal momentum $\vec{k} = 0$. Electron-hole recombination can occur radiatively via single-photon emission, making them ideal for LEDs, laser diodes, and solid-state lighting. In an indirect bandgap semiconductor (e.g., Si, Ge), the conduction band minimum is shifted in $\vec{k}$-space relative to the valence band maximum. Recombination requires the simultaneous emission or absorption of a crystal lattice vibration (phonon) to conserve momentum: making radiative recombination highly inefficient.

3. Intrinsic Carrier Density & The Law of Mass Action

At finite temperature $T > 0\text{ K}$, thermal phonons excite electrons across $E_g$ into the conduction band, leaving behind vacant bonding states in the valence band termed holes. A hole acts dynamically as a mobile carrier with positive elementary charge $+q$ and effective mass $m_h^*$. The probability of electron occupancy at energy $E$ is governed by the Fermi-Dirac distribution: where $E_F$ is the Fermi energy level. In an intrinsic semiconductor, the free electron concentration $n$ in the conduction band and hole concentration $p$ in the valence band are: where $N_C = 2\left(\frac{2\pi m_e^* k_B T}{h^2}\right)^{3/2}$ and $N_V = 2\left(\frac{2\pi m_h^* k_B T}{h^2}\right)^{3/2}$ are the effective density of states. Since each thermal generation creates one electron-hole pair, $n = p = n_i$. Multiplying $n$ and $p$ delivers the fundamental Law of Mass Action: In an intrinsic semiconductor, the intrinsic Fermi level lies almost precisely at mid-gap:

1. Doping & Extrinsic Conduction

To control conductivity, precise trace quantities of impurity atoms (dopants, roughly 1 per $10^5$ to $10^8$ host atoms) are introduced into the host crystal lattice:

• N-Type Semiconductors (Donor Doping): Group 14 elements (Si, Ge) are doped with pentavalent Group 15 impurities (Phosphorus, Arsenic, Antimony). Four valence electrons form covalent bonds with adjacent Si atoms; the fifth electron is loosely bound with small ionization energy ($E_d \approx 0.045\text{ eV}$ below $E_C$). At room temperature, essentially all donor atoms ionize:
  $$n \approx N_D, \quad p = \frac{n_i^2}{N_D} \ll n$$
  Electrons are the majority carriers; holes are the minority carriers. The Fermi level shifts upwards toward the conduction band:
  $$E_F = E_C - k_B T \ln\left( \frac{N_C}{N_D} \right)$$
• P-Type Semiconductors (Acceptor Doping): Doped with trivalent Group 13 impurities (Boron, Gallium, Indium). Three valence electrons form bonds, leaving an unfilled orbital that readily accepts an electron from an adjacent bond, creating a mobile hole with small acceptor ionization energy ($E_a \approx 0.045\text{ eV}$ above $E_V$). At room temperature:
  $$p \approx N_A, \quad n = \frac{n_i^2}{N_A} \ll p$$
  Holes are the majority carriers; electrons are the minority carriers. The Fermi level shifts downward toward the valence band:
  $$E_F = E_V + k_B T \ln\left( \frac{N_V}{N_A} \right)$$

2. Total Conductivity & Temperature Regimes

The electrical conductivity $\sigma$ of an extrinsic semiconductor is determined by carrier concentrations and mobilities $\mu_n, \mu_p$: As temperature increases, extrinsic semiconductors exhibit three distinct regimes:

1. Freeze-out Regime ($T < 100\text{ K}$): Thermal energy is insufficient to ionize all dopants; carrier concentration rises with $T$.
2. Extrinsic / Saturation Regime ($100\text{ K} < T < 450\text{ K}$): All dopants are ionized ($n \approx N_D$), and carrier concentration is nearly constant. Conductivity decreases slightly due to acoustic phonon lattice scattering ($\mu \propto T^{-3/2}$).
3. Intrinsic Regime ($T > 450\text{ K}$): Thermal electron-hole generation across $E_g$ swamps dopant concentration ($n_i \gg N_D$), causing exponential rise in conductivity and loss of semiconductor device functionality.

1. Formation of the Depletion Layer & Built-in Potential

When a P-type and an N-type semiconductor are joined metallurgically, a steep carrier gradient exists across the metallurgical junction. Electrons diffuse from the N-side into the P-side, and holes diffuse from the P-side into the N-side. Near the metallurgical interface, recombining carriers leave behind uncompensated, fixed ionized dopant cores: positively charged donor ions ($N_D^+$) on the N-side, and negatively charged acceptor ions ($N_A^-$) on the P-side. This region devoid of free mobile carriers is termed the depletion layer (or space-charge region). The resulting space-charge density $\rho(x)$ sets up an internal electric field $\vec{\mathcal{E}}$ pointing from N to P that opposes further diffusion. In thermal equilibrium, the diffusion current is exactly balanced by the drift current: Integrating Poisson's equation $\frac{d^2 V}{dx^2} = -\frac{\rho(x)}{\varepsilon}$ across the junction yields the built-in contact potential barrier $V_{bi}$: where $V_T = k_B T / q \approx 25.86\text{ mV}$ at $300\text{ K}$ is the thermal voltage. For typical silicon PN junctions, $V_{bi} \approx 0.65\text{ V} - 0.85\text{ V}$.

2. Depletion Width & Space-Charge Balance

By charge neutrality, the total negative charge per unit area on the P-side must equal the positive charge on the N-side: $q N_A x_p = q N_D x_n$. Under an applied external bias voltage $V$ (positive for forward bias, negative for reverse bias), the effective potential barrier is $V_{bi} - V$. The total depletion width $W = x_n + x_p$ is: Under forward bias ($V > 0$), the barrier lowers to $V_{bi} - V$, shrinking $W$ and enabling massive majority carrier injection. Under reverse bias ($V < 0$), the barrier height increases to $V_{bi} + |V|$, widening the depletion region.

3. The Shockley Ideal Diode Equation

William Shockley (1949) derived the net terminal current by solving the minority carrier diffusion equations in the neutral regions under low-level injection: where $I_s$ is the reverse saturation current, given by: and $\eta$ is the ideality factor ($\eta \approx 1$ for diffusion-dominated conduction, $\eta \approx 2$ when recombination in the depletion layer dominates at low currents). The dynamic (AC) resistance of the forward-biased diode is: At room temperature with $\eta = 1$ and $I = 1\text{ mA}$, $r_d \approx 26\,\Omega$.

1. Half-Wave Rectifier Circuit Analysis

A half-wave rectifier converts AC voltage $v_{\text{in}}(t) = V_m \sin(\omega t)$ into pulsating unidirectional DC by utilizing a single diode in series with load resistor $R_L$. During the positive half-cycle ($0 \le \omega t < \pi$), the diode is forward-biased and conducts with forward diode resistance $r_f$: During the negative half-cycle ($\pi \le \omega t < 2\pi$), the diode is reverse-biased ($i(t) = 0$).

• DC Output Current & Voltage:
  $$I_{dc} = \frac{1}{2\pi} \int_0^\pi I_m \sin(\omega t) d(\omega t) = \frac{I_m}{\pi} \approx 0.318 I_m, \quad V_{dc} = I_{dc} R_L = \frac{V_m}{\pi}$$
• RMS Output Current:
  $$I_{\text{rms}} = \sqrt{ \frac{1}{2\pi} \int_0^\pi I_m^2 \sin^2(\omega t) d(\omega t) } = \frac{I_m}{2} = 0.50 I_m$$
• Rectification Efficiency $\eta_{\text{rec}}$:
  $$\eta = \frac{P_{dc}}{P_{ac}} = \frac{I_{dc}^2 R_L}{I_{\text{rms}}^2 (r_f + R_L)} = \frac{(I_m/\pi)^2 R_L}{(I_m/2)^2 (r_f + R_L)} = \frac{4}{\pi^2} \frac{R_L}{r_f + R_L} \le \frac{4}{\pi^2} \approx 40.6\%$$
• Ripple Factor $r$: Measures AC fluctuation relative to DC:
  $$r = \frac{I_{ac}}{I_{dc}} = \sqrt{ \left(\frac{I_{\text{rms}}}{I_{dc}}\right)^2 - 1 } = \sqrt{ \left(\frac{I_m/2}{I_m/\pi}\right)^2 - 1 } = \sqrt{ \frac{\pi^2}{4} - 1 } \approx 1.21$$
• Peak Inverse Voltage (PIV): Maximum reverse voltage appearing across the diode during the negative half-cycle: $\text{PIV} = V_m$.

2. Full-Wave Center-Tapped & Bridge Rectifiers

A full-wave rectifier conducts on both half-cycles. For a bridge rectifier using four diodes, two diodes conduct alternately during each half-cycle.

• DC Output Current & Voltage:
  $$I_{dc} = \frac{2 I_m}{\pi} \approx 0.637 I_m, \quad V_{dc} = \frac{2 V_m}{\pi}$$
• RMS Output Current:
  $$I_{\text{rms}} = \frac{I_m}{\sqrt{2}} \approx 0.707 I_m$$
• Maximum Efficiency:
  $$\eta = \frac{I_{dc}^2 R_L}{I_{\text{rms}}^2 (2r_f + R_L)} = \frac{(2I_m/\pi)^2}{(I_m/\sqrt{2})^2} = \frac{8}{\pi^2} \approx 81.2\%$$
• Ripple Factor:
  $$r = \sqrt{ \left(\frac{I_{\text{rms}}}{I_{dc}}\right)^2 - 1 } = \sqrt{ \left(\frac{I_m/\sqrt{2}}{2I_m/\pi}\right)^2 - 1 } = \sqrt{ \frac{\pi^2}{8} - 1 } \approx 0.482$$
• Peak Inverse Voltage (PIV):
  • Center-Tapped Full-Wave Rectifier: $\text{PIV} = 2 V_m$.
  • Bridge Rectifier: $\text{PIV} = V_m$ (huge advantage for high-voltage power supplies).
• Fundamental Ripple Frequency: $f_{\text{ripple}} = 2 f_{\text{in}}$ ($100\text{ Hz}$ or $120\text{ Hz}$), making full-wave ripple substantially easier to filter than half-wave ($f_{\text{ripple}} = f_{\text{in}}$).

1. Shunt Capacitor Filter

A capacitor of capacitance $C$ placed in parallel across the load resistor $R_L$ charges to the peak voltage $V_m$ when the rectifier conducts, and discharges slowly through $R_L$ during non-conducting intervals with time constant $\tau = R_L C \gg T/2$. The peak-to-peak ripple voltage $V_{r(pp)}$ is given by: where $f$ is the AC line frequency ($2f$ is the full-wave ripple frequency). The DC output voltage is $V_{dc} = V_m - \frac{V_{r(pp)}}{2} = V_m - \frac{I_{dc}}{4 f C}$. Approximating the triangular ripple waveform by its RMS value $V_{\text{rms, ripple}} = \frac{V_{r(pp)}}{2\sqrt{3}}$, the ripple factor is: Notice that for a capacitor filter, the ripple factor is inversely proportional to $R_L$: as load current increases ($R_L$ decreases), ripple worsens.

2. Series Inductor (Choke) Filter

An inductor of inductance $L$ placed in series with the load opposes changes in current through Faraday's back-EMF. By Fourier analysis of a full-wave rectified wave: At the second harmonic ($2\omega$), the impedance of the inductor is $2\omega L$. For $2\omega L \gg R_L$: Unlike the capacitor filter, the inductor filter ripple factor decreases as load current increases (smaller $R_L$), making it ideal for heavy current applications.

3. Choke-Input L-Section Filter (LC Filter)

Combining a series inductor $L$ and a shunt capacitor $C$: the inductor blocks AC harmonics while the capacitor shunts remaining AC to ground. For $2\omega L \gg \frac{1}{2\omega C}$:

Crucial Property: The ripple factor of an LC filter is completely independent of load resistance $R_L$, providing stable filtering across varying load currents, provided $L$ exceeds the critical inductance $L_c = \frac{R_L}{3\omega}$.

4. Pi-Section (CLC) Filter

A $\pi$-section filter consists of an input shunt capacitor $C_1$, a series choke $L$, and an output shunt capacitor $C_2$. It combines the high DC voltage of the capacitor filter with the superior ripple attenuation of the LC filter: This provides an ultra-low ripple factor ($r < 0.001$) widely used in high-fidelity audio and communication power supplies.

1. Breakdown Mechanisms in Reverse-Biased PN Junctions

When the reverse bias voltage across a PN junction exceeds a critical threshold, the reverse current increases dramatically. Two physical breakdown mechanisms occur:

• Zener Breakdown (Quantum Tunneling): Occurs in heavily doped PN junctions ($N_A, N_D > 10^{18}\text{ cm}^{-3}$) with very narrow depletion regions ($W < 10\text{ nm}$). The intense electric field ($\mathcal{E} > 10^6\text{ V/cm}$) enables valence electrons to quantum tunnel directly into unoccupied conduction band states across the junction. Zener breakdown occurs at low voltages ($V_Z < 5.6\text{ V}$) and has a negative temperature coefficient (breakdown voltage decreases as $T$ increases).
• Avalanche Breakdown (Impact Ionization): Occurs in lightly doped PN junctions with wide depletion regions. The electric field accelerates thermally generated minority carriers to sufficient kinetic energy that they collide with lattice atoms, knocking valence electrons free in an impact ionization cascade. Avalanche breakdown occurs at higher voltages ($V_Z > 5.6\text{ V}$) and has a positive temperature coefficient.

2. Zener Diode Shunt Voltage Regulator Circuit

A Zener diode operated in its reverse breakdown region maintains a nearly constant terminal voltage $V_Z$ across wide variations in input voltage $V_{\text{in}}$ or load current $I_L$. A current-limiting resistor $R_s$ is connected in series between the unregulated DC supply $V_{\text{in}}$ and the parallel combination of the Zener diode and load resistor $R_L$: where $I_L = V_Z / R_L$.

• Condition for Regulation: The Zener current must satisfy $I_{Z(\text{min})} \le I_Z \le I_{Z(\text{max})}$, where $I_{Z(\text{min})}$ (knee current) ensures the diode remains in breakdown, and $I_{Z(\text{max})} = P_{Z(\text{max})} / V_Z$ prevents thermal destruction.
• Design Formula for Series Resistor $R_s$:
  $$R_{s(\text{max})} = \frac{V_{\text{in}(\text{min})} - V_Z}{I_L(\text{max}) + I_{Z(\text{min})}}, \quad R_{s(\text{min})} = \frac{V_{\text{in}(\text{max})} - V_Z}{I_L(\text{min}) + I_{Z(\text{max})}}$$
• Line Regulation & Load Regulation: Line regulation measures output stability against input fluctuations $\frac{\Delta V_L}{\Delta V_{\text{in}}} = \frac{r_z}{R_s + r_z}$, where $r_z$ is the dynamic Zener resistance. Load regulation measures output drop as load current increases: $\frac{\Delta V_L}{\Delta I_L} = -(r_z \parallel R_s) \approx -r_z$.