§6.1 ROMs, RAMs and address decoding

Unit 6, Lesson 1: ROMs, RAMs and address decoding

Learning focus: Address bits select storage locations; data widths establish the number of bits per location. ROM contents are fixed for a session; RAM may update in response to writes.

1. The idea in engineering context

Address bits select storage locations; data widths establish the number of bits per location. ROM contents are fixed for a session; RAM may update in response to writes. This principle belongs within memory, programmable logic and datapaths. To reason correctly, decide what kind of object each symbol represents: a Boolean truth value, a signed integer, a sample of a waveform, a device threshold, a state bit, or a timed event. An equation may be mathematically valid yet describe the wrong physical or temporal quantity. In a circuit drawing, label all inputs, outputs and control signals with direction and active polarity. If a signal can be unknown, undefined or invalid, describe what the receiving block must do rather than silently treating the signal as zero.

A useful preliminary step is to state the behavior without naming any particular component. For the topic roms, rams and address decoding, write an input-output contract in plain language and translate it to a truth table, transition table, numerical equation or timing diagram as appropriate. The same contract should survive translation into a schematic, a behavioral simulation and an HDL module. If an implementation changes the contract, the change must be documented as a new requirement rather than hidden as a convenience.

2. A checkable example

A 1K×8 memory stores 1024 bytes, or 8192 bits, and requires ten address bits. Reproduce this calculation or Boolean reasoning from the definitions, showing intermediate bit patterns and units where relevant. When the example uses an idealized value, state explicitly that the numerical values are illustrative teaching inputs, not component specifications. If it refers to a word length, compute the representable range; if it refers to timing, identify the relevant clock domain, edge and uncertainty terms; and if it refers to a voltage, distinguish absolute maximum ratings from guaranteed digital logic levels.

Alternate check. Explain the expected result qualitatively before computing it. A binary carry chain, parity function, or state transition often has an intuitive conserved property: changing one input can affect a particular output but not every unrelated output. Compare the intuitive expectation with the mathematical answer and resolve discrepancies by writing a smaller exhaustive example. This is especially important when signed interpretation, bit ordering or active-low conventions may reverse an apparently obvious answer.

3. Design method and derivation

Controller reasoning. A design is easier to verify when the number of states and their meaning are explicit. For every state, define outputs, permitted next states and conditions for remaining in place. Write the illegal-state behavior in addition to the nominal transition graph. Test whether a requested action is lost during reset or when two requests arrive together. Safety properties and liveness properties must be stated separately; one forbids bad events, the other asks that desired events eventually occur.

The next step is to make the dependence of output on input explicit. Start with the simplest special case: zero data, inactive enable, reset asserted, or minimum address as appropriate. Then test the opposite boundary, including all-one words, maximum carry, saturated load, or final counter state. For roms, rams and address decoding, list which of these tests are informative and which are irrelevant. Do not automatically assign meaning to a don't-care or illegal combination. If a simplification assumes certain input codes never occur, describe how the enclosing system enforces that assumption.

Memory and width discipline. Record whether the unit reads or writes on the active edge, whether outputs are combinational or registered, and what an address means in bytes or words. The width of intermediate arithmetic can change the computed result even when the mathematical expression looks correct. Where hardware behavior is device-specific, include explicit assumptions and avoid relying on simulator defaults. Test first and last valid addresses and deliberately malformed transactions.

4. Failure modes and limits

Topic-specific pitfall: Byte and word addressing are different conventions; mixing them shifts memory locations. A reliable engineering write-up names the condition that triggers the failure, the observable symptom and the quickest discriminating test. For a functional bug, compare expected and actual truth-table rows; for a timing bug, inspect waveform edges and clock assumptions; for a numeric bug, inspect sign extension and intermediate widths; and for an interface bug, check whether validity and acknowledgement share the same interpretation at each endpoint.

Unit-level model boundary: Memory read-during-write behavior and FPGA inference details differ across implementations; do not assume universal semantics. Avoid extrapolating an ideal gate model into a claim about any particular commercial part. Robustness also requires considering reset entry, temperature-dependent device performance and asynchronous external disturbances whenever they are relevant. If a measured device disagrees with a model, first verify the input stimulus, measurement bandwidth and grounding before declaring the underlying logic theory incorrect.

5. Worked design workflow

1. Specify: write a sentence that defines each input, output and its width; resolve any ambiguous invalid or simultaneous input behavior.

2. Model: select a Boolean expression, transition relation or time equation that captures the defined behavior and state all assumptions.

3. Derive: compute the result for the particular illustrative case above. If there is arithmetic, keep bit widths explicit through every intermediate operation.

4. Cross-check: compare against an independently enumerated case or a direct formula. Document discrepancies rather than adjusting the expected answer to match the implementation.

5. Implement: map the model to gates or synthesizable RTL, leaving enough information to identify clocking, reset and active polarities.

6. Verify: test boundaries and one deliberate fault injection, then record whether the result is logical, simulated, measured or formally proven.

This workflow is intentionally stricter than drawing a plausible diagram. An executable calculator can confirm arithmetic while missing an incorrect interpretation of its inputs. Conversely, a timing waveform can look convincing even if the specification omitted a simultaneous request. A successful solution must connect intent, derivation and independent observation.

6. Laboratory and simulation protocol

Investigation: Compute capacity, width and address range for three hypothetical memories. Construct a small input matrix containing at least one nominal case, a lower boundary, an upper boundary and a deliberately ambiguous or invalid stimulus. Before running a browser model, write your predicted output and the rule that supports it. Run the experiment, record the output and compare. If the model disagrees with your prediction, determine whether the error is in your rule, your convention, or the model. Explicitly distinguish calculated values from observed electrical measurements; the provided browser apps are not instruments connected to hardware.

Extensions. Repeat the test with an input changed by one bit or one clock cycle. If the result is unchanged, explain which invariance made that possible. If the result changes, identify the exact dependency path. Next ask whether this exercise would still work with a real gate driving several receivers, a different supply voltage, or a clock with uncertainty. That question may require a data sheet, timing analysis or physical measurement beyond the ideal simulation.

7. Guided exercises

1. Derive and explain. Starting from the definition behind roms, rams and address decoding, construct the smallest nontrivial truth table, bit pattern, timing diagram or state-transition example. Label all relevant conventions. Provide an independent cross-check.

2. Boundary case. Modify the worked example so that one parameter is at its legal minimum and another at its legal maximum. Recompute the expected result and explain whether the nominal assumption still holds.

3. Find the error. Analyze this claim: “Byte and word addressing are different conventions; mixing them shifts memory locations.” Identify a concrete input condition that reveals the problem, describe the output symptom and propose a correction or safety guard.

4. Design choice. Compare two implementations of the lesson's function: a direct gate-level representation and a modular block with explicit interface signals. State their likely advantages in clarity, area, timing or testability without assuming a universal winner.

5. Verification. Write five test vectors (including a boundary and invalid input), expected results and a single assertion or invariant that should hold across the set. Explain how a false-positive test could occur.

8. Reflection and further study

The central question of ROMs, RAMs and address decoding is not whether an expression looks familiar, but whether a particular result follows from a complete set of stated assumptions. Recheck the significance of each bit and event, the boundary conditions and the consequences of implementing the abstraction in physical hardware. In design reviews, a clearly documented failed assumption is more valuable than a visually polished schematic with hidden undefined behavior. Before moving on, write a three-sentence summary: what this mechanism guarantees, what it does not guarantee, and the simplest independent test that would reveal a mistake.

§6.2 Memory read and write timing

Unit 6, Lesson 2: Memory read and write timing

Learning focus: A synchronous memory can deliver data on a clock boundary rather than combinationally. Read-during-write behavior is implementation-dependent unless specified.

1. The idea in engineering context

A synchronous memory can deliver data on a clock boundary rather than combinationally. Read-during-write behavior is implementation-dependent unless specified. This principle belongs within memory, programmable logic and datapaths. To reason correctly, decide what kind of object each symbol represents: a Boolean truth value, a signed integer, a sample of a waveform, a device threshold, a state bit, or a timed event. An equation may be mathematically valid yet describe the wrong physical or temporal quantity. In a circuit drawing, label all inputs, outputs and control signals with direction and active polarity. If a signal can be unknown, undefined or invalid, describe what the receiving block must do rather than silently treating the signal as zero.

A useful preliminary step is to state the behavior without naming any particular component. For the topic memory read and write timing, write an input-output contract in plain language and translate it to a truth table, transition table, numerical equation or timing diagram as appropriate. The same contract should survive translation into a schematic, a behavioral simulation and an HDL module. If an implementation changes the contract, the change must be documented as a new requirement rather than hidden as a convenience.

2. A checkable example

A one-cycle-read-latency RAM addressed at rising edge n delivers the requested data at a defined later edge according to its interface contract. Reproduce this calculation or Boolean reasoning from the definitions, showing intermediate bit patterns and units where relevant. When the example uses an idealized value, state explicitly that the numerical values are illustrative teaching inputs, not component specifications. If it refers to a word length, compute the representable range; if it refers to timing, identify the relevant clock domain, edge and uncertainty terms; and if it refers to a voltage, distinguish absolute maximum ratings from guaranteed digital logic levels.

Alternate check. Explain the expected result qualitatively before computing it. A binary carry chain, parity function, or state transition often has an intuitive conserved property: changing one input can affect a particular output but not every unrelated output. Compare the intuitive expectation with the mathematical answer and resolve discrepancies by writing a smaller exhaustive example. This is especially important when signed interpretation, bit ordering or active-low conventions may reverse an apparently obvious answer.

3. Design method and derivation

Controller reasoning. A design is easier to verify when the number of states and their meaning are explicit. For every state, define outputs, permitted next states and conditions for remaining in place. Write the illegal-state behavior in addition to the nominal transition graph. Test whether a requested action is lost during reset or when two requests arrive together. Safety properties and liveness properties must be stated separately; one forbids bad events, the other asks that desired events eventually occur.

The next step is to make the dependence of output on input explicit. Start with the simplest special case: zero data, inactive enable, reset asserted, or minimum address as appropriate. Then test the opposite boundary, including all-one words, maximum carry, saturated load, or final counter state. For memory read and write timing, list which of these tests are informative and which are irrelevant. Do not automatically assign meaning to a don't-care or illegal combination. If a simplification assumes certain input codes never occur, describe how the enclosing system enforces that assumption.

Memory and width discipline. Record whether the unit reads or writes on the active edge, whether outputs are combinational or registered, and what an address means in bytes or words. The width of intermediate arithmetic can change the computed result even when the mathematical expression looks correct. Where hardware behavior is device-specific, include explicit assumptions and avoid relying on simulator defaults. Test first and last valid addresses and deliberately malformed transactions.

4. Failure modes and limits

Topic-specific pitfall: A textbook array indexed by an address is not sufficient to model a physical SRAM timing protocol. A reliable engineering write-up names the condition that triggers the failure, the observable symptom and the quickest discriminating test. For a functional bug, compare expected and actual truth-table rows; for a timing bug, inspect waveform edges and clock assumptions; for a numeric bug, inspect sign extension and intermediate widths; and for an interface bug, check whether validity and acknowledgement share the same interpretation at each endpoint.

Unit-level model boundary: Memory read-during-write behavior and FPGA inference details differ across implementations; do not assume universal semantics. Avoid extrapolating an ideal gate model into a claim about any particular commercial part. Robustness also requires considering reset entry, temperature-dependent device performance and asynchronous external disturbances whenever they are relevant. If a measured device disagrees with a model, first verify the input stimulus, measurement bandwidth and grounding before declaring the underlying logic theory incorrect.

5. Worked design workflow

1. Specify: write a sentence that defines each input, output and its width; resolve any ambiguous invalid or simultaneous input behavior.

2. Model: select a Boolean expression, transition relation or time equation that captures the defined behavior and state all assumptions.

3. Derive: compute the result for the particular illustrative case above. If there is arithmetic, keep bit widths explicit through every intermediate operation.

4. Cross-check: compare against an independently enumerated case or a direct formula. Document discrepancies rather than adjusting the expected answer to match the implementation.

5. Implement: map the model to gates or synthesizable RTL, leaving enough information to identify clocking, reset and active polarities.

6. Verify: test boundaries and one deliberate fault injection, then record whether the result is logical, simulated, measured or formally proven.

This workflow is intentionally stricter than drawing a plausible diagram. An executable calculator can confirm arithmetic while missing an incorrect interpretation of its inputs. Conversely, a timing waveform can look convincing even if the specification omitted a simultaneous request. A successful solution must connect intent, derivation and independent observation.

6. Laboratory and simulation protocol

Investigation: Write an access table with clock edge, address, write enable, data-in and expected data-out. Construct a small input matrix containing at least one nominal case, a lower boundary, an upper boundary and a deliberately ambiguous or invalid stimulus. Before running a browser model, write your predicted output and the rule that supports it. Run the experiment, record the output and compare. If the model disagrees with your prediction, determine whether the error is in your rule, your convention, or the model. Explicitly distinguish calculated values from observed electrical measurements; the provided browser apps are not instruments connected to hardware.

Extensions. Repeat the test with an input changed by one bit or one clock cycle. If the result is unchanged, explain which invariance made that possible. If the result changes, identify the exact dependency path. Next ask whether this exercise would still work with a real gate driving several receivers, a different supply voltage, or a clock with uncertainty. That question may require a data sheet, timing analysis or physical measurement beyond the ideal simulation.

7. Guided exercises

1. Derive and explain. Starting from the definition behind memory read and write timing, construct the smallest nontrivial truth table, bit pattern, timing diagram or state-transition example. Label all relevant conventions. Provide an independent cross-check.

2. Boundary case. Modify the worked example so that one parameter is at its legal minimum and another at its legal maximum. Recompute the expected result and explain whether the nominal assumption still holds.

3. Find the error. Analyze this claim: “A textbook array indexed by an address is not sufficient to model a physical SRAM timing protocol.” Identify a concrete input condition that reveals the problem, describe the output symptom and propose a correction or safety guard.

4. Design choice. Compare two implementations of the lesson's function: a direct gate-level representation and a modular block with explicit interface signals. State their likely advantages in clarity, area, timing or testability without assuming a universal winner.

5. Verification. Write five test vectors (including a boundary and invalid input), expected results and a single assertion or invariant that should hold across the set. Explain how a false-positive test could occur.

8. Reflection and further study

The central question of Memory read and write timing is not whether an expression looks familiar, but whether a particular result follows from a complete set of stated assumptions. Recheck the significance of each bit and event, the boundary conditions and the consequences of implementing the abstraction in physical hardware. In design reviews, a clearly documented failed assumption is more valuable than a visually polished schematic with hidden undefined behavior. Before moving on, write a three-sentence summary: what this mechanism guarantees, what it does not guarantee, and the simplest independent test that would reveal a mistake.

§6.3 Programmable logic and LUTs

Unit 6, Lesson 3: Programmable logic and LUTs

Learning focus: An FPGA LUT stores truth-table bits implementing a configurable function, while flip-flops and routing define registered datapaths and timing.

1. The idea in engineering context

An FPGA LUT stores truth-table bits implementing a configurable function, while flip-flops and routing define registered datapaths and timing. This principle belongs within memory, programmable logic and datapaths. To reason correctly, decide what kind of object each symbol represents: a Boolean truth value, a signed integer, a sample of a waveform, a device threshold, a state bit, or a timed event. An equation may be mathematically valid yet describe the wrong physical or temporal quantity. In a circuit drawing, label all inputs, outputs and control signals with direction and active polarity. If a signal can be unknown, undefined or invalid, describe what the receiving block must do rather than silently treating the signal as zero.

A useful preliminary step is to state the behavior without naming any particular component. For the topic programmable logic and luts, write an input-output contract in plain language and translate it to a truth table, transition table, numerical equation or timing diagram as appropriate. The same contract should survive translation into a schematic, a behavioral simulation and an HDL module. If an implementation changes the contract, the change must be documented as a new requirement rather than hidden as a convenience.

2. A checkable example

A four-input LUT has 16 truth-table entries and can implement any single-output Boolean function of four inputs. Reproduce this calculation or Boolean reasoning from the definitions, showing intermediate bit patterns and units where relevant. When the example uses an idealized value, state explicitly that the numerical values are illustrative teaching inputs, not component specifications. If it refers to a word length, compute the representable range; if it refers to timing, identify the relevant clock domain, edge and uncertainty terms; and if it refers to a voltage, distinguish absolute maximum ratings from guaranteed digital logic levels.

Alternate check. Explain the expected result qualitatively before computing it. A binary carry chain, parity function, or state transition often has an intuitive conserved property: changing one input can affect a particular output but not every unrelated output. Compare the intuitive expectation with the mathematical answer and resolve discrepancies by writing a smaller exhaustive example. This is especially important when signed interpretation, bit ordering or active-low conventions may reverse an apparently obvious answer.

3. Design method and derivation

Controller reasoning. A design is easier to verify when the number of states and their meaning are explicit. For every state, define outputs, permitted next states and conditions for remaining in place. Write the illegal-state behavior in addition to the nominal transition graph. Test whether a requested action is lost during reset or when two requests arrive together. Safety properties and liveness properties must be stated separately; one forbids bad events, the other asks that desired events eventually occur.

The next step is to make the dependence of output on input explicit. Start with the simplest special case: zero data, inactive enable, reset asserted, or minimum address as appropriate. Then test the opposite boundary, including all-one words, maximum carry, saturated load, or final counter state. For programmable logic and luts, list which of these tests are informative and which are irrelevant. Do not automatically assign meaning to a don't-care or illegal combination. If a simplification assumes certain input codes never occur, describe how the enclosing system enforces that assumption.

Memory and width discipline. Record whether the unit reads or writes on the active edge, whether outputs are combinational or registered, and what an address means in bytes or words. The width of intermediate arithmetic can change the computed result even when the mathematical expression looks correct. Where hardware behavior is device-specific, include explicit assumptions and avoid relying on simulator defaults. Test first and last valid addresses and deliberately malformed transactions.

4. Failure modes and limits

Topic-specific pitfall: FPGA timing is dominated by placement and routing as well as LUT logic depth. A reliable engineering write-up names the condition that triggers the failure, the observable symptom and the quickest discriminating test. For a functional bug, compare expected and actual truth-table rows; for a timing bug, inspect waveform edges and clock assumptions; for a numeric bug, inspect sign extension and intermediate widths; and for an interface bug, check whether validity and acknowledgement share the same interpretation at each endpoint.

Unit-level model boundary: Memory read-during-write behavior and FPGA inference details differ across implementations; do not assume universal semantics. Avoid extrapolating an ideal gate model into a claim about any particular commercial part. Robustness also requires considering reset entry, temperature-dependent device performance and asynchronous external disturbances whenever they are relevant. If a measured device disagrees with a model, first verify the input stimulus, measurement bandwidth and grounding before declaring the underlying logic theory incorrect.

5. Worked design workflow

1. Specify: write a sentence that defines each input, output and its width; resolve any ambiguous invalid or simultaneous input behavior.

2. Model: select a Boolean expression, transition relation or time equation that captures the defined behavior and state all assumptions.

3. Derive: compute the result for the particular illustrative case above. If there is arithmetic, keep bit widths explicit through every intermediate operation.

4. Cross-check: compare against an independently enumerated case or a direct formula. Document discrepancies rather than adjusting the expected answer to match the implementation.

5. Implement: map the model to gates or synthesizable RTL, leaving enough information to identify clocking, reset and active polarities.

6. Verify: test boundaries and one deliberate fault injection, then record whether the result is logical, simulated, measured or formally proven.

This workflow is intentionally stricter than drawing a plausible diagram. An executable calculator can confirm arithmetic while missing an incorrect interpretation of its inputs. Conversely, a timing waveform can look convincing even if the specification omitted a simultaneous request. A successful solution must connect intent, derivation and independent observation.

6. Laboratory and simulation protocol

Investigation: Implement a four-input Boolean function using a LUT truth table. Construct a small input matrix containing at least one nominal case, a lower boundary, an upper boundary and a deliberately ambiguous or invalid stimulus. Before running a browser model, write your predicted output and the rule that supports it. Run the experiment, record the output and compare. If the model disagrees with your prediction, determine whether the error is in your rule, your convention, or the model. Explicitly distinguish calculated values from observed electrical measurements; the provided browser apps are not instruments connected to hardware.

Extensions. Repeat the test with an input changed by one bit or one clock cycle. If the result is unchanged, explain which invariance made that possible. If the result changes, identify the exact dependency path. Next ask whether this exercise would still work with a real gate driving several receivers, a different supply voltage, or a clock with uncertainty. That question may require a data sheet, timing analysis or physical measurement beyond the ideal simulation.

7. Guided exercises

1. Derive and explain. Starting from the definition behind programmable logic and luts, construct the smallest nontrivial truth table, bit pattern, timing diagram or state-transition example. Label all relevant conventions. Provide an independent cross-check.

2. Boundary case. Modify the worked example so that one parameter is at its legal minimum and another at its legal maximum. Recompute the expected result and explain whether the nominal assumption still holds.

3. Find the error. Analyze this claim: “FPGA timing is dominated by placement and routing as well as LUT logic depth.” Identify a concrete input condition that reveals the problem, describe the output symptom and propose a correction or safety guard.

4. Design choice. Compare two implementations of the lesson's function: a direct gate-level representation and a modular block with explicit interface signals. State their likely advantages in clarity, area, timing or testability without assuming a universal winner.

5. Verification. Write five test vectors (including a boundary and invalid input), expected results and a single assertion or invariant that should hold across the set. Explain how a false-positive test could occur.

8. Reflection and further study

The central question of Programmable logic and LUTs is not whether an expression looks familiar, but whether a particular result follows from a complete set of stated assumptions. Recheck the significance of each bit and event, the boundary conditions and the consequences of implementing the abstraction in physical hardware. In design reviews, a clearly documented failed assumption is more valuable than a visually polished schematic with hidden undefined behavior. Before moving on, write a three-sentence summary: what this mechanism guarantees, what it does not guarantee, and the simplest independent test that would reveal a mistake.

§6.4 Datapath widths, signedness and saturation

Unit 6, Lesson 4: Datapath widths, signedness and saturation

Learning focus: Fixed-width arithmetic is modular by default in many hardware contexts. Saturation arithmetic requires explicit overflow detection and clipping logic.

1. The idea in engineering context

Fixed-width arithmetic is modular by default in many hardware contexts. Saturation arithmetic requires explicit overflow detection and clipping logic. This principle belongs within memory, programmable logic and datapaths. To reason correctly, decide what kind of object each symbol represents: a Boolean truth value, a signed integer, a sample of a waveform, a device threshold, a state bit, or a timed event. An equation may be mathematically valid yet describe the wrong physical or temporal quantity. In a circuit drawing, label all inputs, outputs and control signals with direction and active polarity. If a signal can be unknown, undefined or invalid, describe what the receiving block must do rather than silently treating the signal as zero.

A useful preliminary step is to state the behavior without naming any particular component. For the topic datapath widths, signedness and saturation, write an input-output contract in plain language and translate it to a truth table, transition table, numerical equation or timing diagram as appropriate. The same contract should survive translation into a schematic, a behavioral simulation and an HDL module. If an implementation changes the contract, the change must be documented as a new requirement rather than hidden as a convenience.

2. A checkable example

For 8-bit unsigned arithmetic, 250+20 wraps to 14 modulo 256; saturating addition would output 255. Reproduce this calculation or Boolean reasoning from the definitions, showing intermediate bit patterns and units where relevant. When the example uses an idealized value, state explicitly that the numerical values are illustrative teaching inputs, not component specifications. If it refers to a word length, compute the representable range; if it refers to timing, identify the relevant clock domain, edge and uncertainty terms; and if it refers to a voltage, distinguish absolute maximum ratings from guaranteed digital logic levels.

Alternate check. Explain the expected result qualitatively before computing it. A binary carry chain, parity function, or state transition often has an intuitive conserved property: changing one input can affect a particular output but not every unrelated output. Compare the intuitive expectation with the mathematical answer and resolve discrepancies by writing a smaller exhaustive example. This is especially important when signed interpretation, bit ordering or active-low conventions may reverse an apparently obvious answer.

3. Design method and derivation

Controller reasoning. A design is easier to verify when the number of states and their meaning are explicit. For every state, define outputs, permitted next states and conditions for remaining in place. Write the illegal-state behavior in addition to the nominal transition graph. Test whether a requested action is lost during reset or when two requests arrive together. Safety properties and liveness properties must be stated separately; one forbids bad events, the other asks that desired events eventually occur.

The next step is to make the dependence of output on input explicit. Start with the simplest special case: zero data, inactive enable, reset asserted, or minimum address as appropriate. Then test the opposite boundary, including all-one words, maximum carry, saturated load, or final counter state. For datapath widths, signedness and saturation, list which of these tests are informative and which are irrelevant. Do not automatically assign meaning to a don't-care or illegal combination. If a simplification assumes certain input codes never occur, describe how the enclosing system enforces that assumption.

Memory and width discipline. Record whether the unit reads or writes on the active edge, whether outputs are combinational or registered, and what an address means in bytes or words. The width of intermediate arithmetic can change the computed result even when the mathematical expression looks correct. Where hardware behavior is device-specific, include explicit assumptions and avoid relying on simulator defaults. Test first and last valid addresses and deliberately malformed transactions.

4. Failure modes and limits

Topic-specific pitfall: Silent truncation can turn a plausible intermediate result into a wrong final measurement. A reliable engineering write-up names the condition that triggers the failure, the observable symptom and the quickest discriminating test. For a functional bug, compare expected and actual truth-table rows; for a timing bug, inspect waveform edges and clock assumptions; for a numeric bug, inspect sign extension and intermediate widths; and for an interface bug, check whether validity and acknowledgement share the same interpretation at each endpoint.

Unit-level model boundary: Memory read-during-write behavior and FPGA inference details differ across implementations; do not assume universal semantics. Avoid extrapolating an ideal gate model into a claim about any particular commercial part. Robustness also requires considering reset entry, temperature-dependent device performance and asynchronous external disturbances whenever they are relevant. If a measured device disagrees with a model, first verify the input stimulus, measurement bandwidth and grounding before declaring the underlying logic theory incorrect.

5. Worked design workflow

1. Specify: write a sentence that defines each input, output and its width; resolve any ambiguous invalid or simultaneous input behavior.

2. Model: select a Boolean expression, transition relation or time equation that captures the defined behavior and state all assumptions.

3. Derive: compute the result for the particular illustrative case above. If there is arithmetic, keep bit widths explicit through every intermediate operation.

4. Cross-check: compare against an independently enumerated case or a direct formula. Document discrepancies rather than adjusting the expected answer to match the implementation.

5. Implement: map the model to gates or synthesizable RTL, leaving enough information to identify clocking, reset and active polarities.

6. Verify: test boundaries and one deliberate fault injection, then record whether the result is logical, simulated, measured or formally proven.

This workflow is intentionally stricter than drawing a plausible diagram. An executable calculator can confirm arithmetic while missing an incorrect interpretation of its inputs. Conversely, a timing waveform can look convincing even if the specification omitted a simultaneous request. A successful solution must connect intent, derivation and independent observation.

6. Laboratory and simulation protocol

Investigation: Design one signed and one unsigned saturating adder and test both extremes. Construct a small input matrix containing at least one nominal case, a lower boundary, an upper boundary and a deliberately ambiguous or invalid stimulus. Before running a browser model, write your predicted output and the rule that supports it. Run the experiment, record the output and compare. If the model disagrees with your prediction, determine whether the error is in your rule, your convention, or the model. Explicitly distinguish calculated values from observed electrical measurements; the provided browser apps are not instruments connected to hardware.

Extensions. Repeat the test with an input changed by one bit or one clock cycle. If the result is unchanged, explain which invariance made that possible. If the result changes, identify the exact dependency path. Next ask whether this exercise would still work with a real gate driving several receivers, a different supply voltage, or a clock with uncertainty. That question may require a data sheet, timing analysis or physical measurement beyond the ideal simulation.

7. Guided exercises

1. Derive and explain. Starting from the definition behind datapath widths, signedness and saturation, construct the smallest nontrivial truth table, bit pattern, timing diagram or state-transition example. Label all relevant conventions. Provide an independent cross-check.

2. Boundary case. Modify the worked example so that one parameter is at its legal minimum and another at its legal maximum. Recompute the expected result and explain whether the nominal assumption still holds.

3. Find the error. Analyze this claim: “Silent truncation can turn a plausible intermediate result into a wrong final measurement.” Identify a concrete input condition that reveals the problem, describe the output symptom and propose a correction or safety guard.

4. Design choice. Compare two implementations of the lesson's function: a direct gate-level representation and a modular block with explicit interface signals. State their likely advantages in clarity, area, timing or testability without assuming a universal winner.

5. Verification. Write five test vectors (including a boundary and invalid input), expected results and a single assertion or invariant that should hold across the set. Explain how a false-positive test could occur.

8. Reflection and further study

The central question of Datapath widths, signedness and saturation is not whether an expression looks familiar, but whether a particular result follows from a complete set of stated assumptions. Recheck the significance of each bit and event, the boundary conditions and the consequences of implementing the abstraction in physical hardware. In design reviews, a clearly documented failed assumption is more valuable than a visually polished schematic with hidden undefined behavior. Before moving on, write a three-sentence summary: what this mechanism guarantees, what it does not guarantee, and the simplest independent test that would reveal a mistake.

§6.5 Bus interfaces and register maps

Unit 6, Lesson 5: Bus interfaces and register maps

Learning focus: A bus transaction has address, control, timing and data meaning. A control register should specify read/write behavior and reserved-bit handling.

1. The idea in engineering context

A bus transaction has address, control, timing and data meaning. A control register should specify read/write behavior and reserved-bit handling. This principle belongs within memory, programmable logic and datapaths. To reason correctly, decide what kind of object each symbol represents: a Boolean truth value, a signed integer, a sample of a waveform, a device threshold, a state bit, or a timed event. An equation may be mathematically valid yet describe the wrong physical or temporal quantity. In a circuit drawing, label all inputs, outputs and control signals with direction and active polarity. If a signal can be unknown, undefined or invalid, describe what the receiving block must do rather than silently treating the signal as zero.

A useful preliminary step is to state the behavior without naming any particular component. For the topic bus interfaces and register maps, write an input-output contract in plain language and translate it to a truth table, transition table, numerical equation or timing diagram as appropriate. The same contract should survive translation into a schematic, a behavioral simulation and an HDL module. If an implementation changes the contract, the change must be documented as a new requirement rather than hidden as a convenience.

2. A checkable example

If a 32-bit register is at byte address 0x1000, the next naturally aligned word register starts at 0x1004. Reproduce this calculation or Boolean reasoning from the definitions, showing intermediate bit patterns and units where relevant. When the example uses an idealized value, state explicitly that the numerical values are illustrative teaching inputs, not component specifications. If it refers to a word length, compute the representable range; if it refers to timing, identify the relevant clock domain, edge and uncertainty terms; and if it refers to a voltage, distinguish absolute maximum ratings from guaranteed digital logic levels.

Alternate check. Explain the expected result qualitatively before computing it. A binary carry chain, parity function, or state transition often has an intuitive conserved property: changing one input can affect a particular output but not every unrelated output. Compare the intuitive expectation with the mathematical answer and resolve discrepancies by writing a smaller exhaustive example. This is especially important when signed interpretation, bit ordering or active-low conventions may reverse an apparently obvious answer.

3. Design method and derivation

Controller reasoning. A design is easier to verify when the number of states and their meaning are explicit. For every state, define outputs, permitted next states and conditions for remaining in place. Write the illegal-state behavior in addition to the nominal transition graph. Test whether a requested action is lost during reset or when two requests arrive together. Safety properties and liveness properties must be stated separately; one forbids bad events, the other asks that desired events eventually occur.

The next step is to make the dependence of output on input explicit. Start with the simplest special case: zero data, inactive enable, reset asserted, or minimum address as appropriate. Then test the opposite boundary, including all-one words, maximum carry, saturated load, or final counter state. For bus interfaces and register maps, list which of these tests are informative and which are irrelevant. Do not automatically assign meaning to a don't-care or illegal combination. If a simplification assumes certain input codes never occur, describe how the enclosing system enforces that assumption.

Memory and width discipline. Record whether the unit reads or writes on the active edge, whether outputs are combinational or registered, and what an address means in bytes or words. The width of intermediate arithmetic can change the computed result even when the mathematical expression looks correct. Where hardware behavior is device-specific, include explicit assumptions and avoid relying on simulator defaults. Test first and last valid addresses and deliberately malformed transactions.

4. Failure modes and limits

Topic-specific pitfall: An interface that lacks handshaking may lose requests under backpressure. A reliable engineering write-up names the condition that triggers the failure, the observable symptom and the quickest discriminating test. For a functional bug, compare expected and actual truth-table rows; for a timing bug, inspect waveform edges and clock assumptions; for a numeric bug, inspect sign extension and intermediate widths; and for an interface bug, check whether validity and acknowledgement share the same interpretation at each endpoint.

Unit-level model boundary: Memory read-during-write behavior and FPGA inference details differ across implementations; do not assume universal semantics. Avoid extrapolating an ideal gate model into a claim about any particular commercial part. Robustness also requires considering reset entry, temperature-dependent device performance and asynchronous external disturbances whenever they are relevant. If a measured device disagrees with a model, first verify the input stimulus, measurement bandwidth and grounding before declaring the underlying logic theory incorrect.

5. Worked design workflow

1. Specify: write a sentence that defines each input, output and its width; resolve any ambiguous invalid or simultaneous input behavior.

2. Model: select a Boolean expression, transition relation or time equation that captures the defined behavior and state all assumptions.

3. Derive: compute the result for the particular illustrative case above. If there is arithmetic, keep bit widths explicit through every intermediate operation.

4. Cross-check: compare against an independently enumerated case or a direct formula. Document discrepancies rather than adjusting the expected answer to match the implementation.

5. Implement: map the model to gates or synthesizable RTL, leaving enough information to identify clocking, reset and active polarities.

6. Verify: test boundaries and one deliberate fault injection, then record whether the result is logical, simulated, measured or formally proven.

This workflow is intentionally stricter than drawing a plausible diagram. An executable calculator can confirm arithmetic while missing an incorrect interpretation of its inputs. Conversely, a timing waveform can look convincing even if the specification omitted a simultaneous request. A successful solution must connect intent, derivation and independent observation.

6. Laboratory and simulation protocol

Investigation: Draw the minimal register map for a timer with control, period and status registers. Construct a small input matrix containing at least one nominal case, a lower boundary, an upper boundary and a deliberately ambiguous or invalid stimulus. Before running a browser model, write your predicted output and the rule that supports it. Run the experiment, record the output and compare. If the model disagrees with your prediction, determine whether the error is in your rule, your convention, or the model. Explicitly distinguish calculated values from observed electrical measurements; the provided browser apps are not instruments connected to hardware.

Extensions. Repeat the test with an input changed by one bit or one clock cycle. If the result is unchanged, explain which invariance made that possible. If the result changes, identify the exact dependency path. Next ask whether this exercise would still work with a real gate driving several receivers, a different supply voltage, or a clock with uncertainty. That question may require a data sheet, timing analysis or physical measurement beyond the ideal simulation.

7. Guided exercises

1. Derive and explain. Starting from the definition behind bus interfaces and register maps, construct the smallest nontrivial truth table, bit pattern, timing diagram or state-transition example. Label all relevant conventions. Provide an independent cross-check.

2. Boundary case. Modify the worked example so that one parameter is at its legal minimum and another at its legal maximum. Recompute the expected result and explain whether the nominal assumption still holds.

3. Find the error. Analyze this claim: “An interface that lacks handshaking may lose requests under backpressure.” Identify a concrete input condition that reveals the problem, describe the output symptom and propose a correction or safety guard.

4. Design choice. Compare two implementations of the lesson's function: a direct gate-level representation and a modular block with explicit interface signals. State their likely advantages in clarity, area, timing or testability without assuming a universal winner.

5. Verification. Write five test vectors (including a boundary and invalid input), expected results and a single assertion or invariant that should hold across the set. Explain how a false-positive test could occur.

8. Reflection and further study

The central question of Bus interfaces and register maps is not whether an expression looks familiar, but whether a particular result follows from a complete set of stated assumptions. Recheck the significance of each bit and event, the boundary conditions and the consequences of implementing the abstraction in physical hardware. In design reviews, a clearly documented failed assumption is more valuable than a visually polished schematic with hidden undefined behavior. Before moving on, write a three-sentence summary: what this mechanism guarantees, what it does not guarantee, and the simplest independent test that would reveal a mistake.