§7.1 Clock period, jitter and skew

Unit 7, Lesson 1: Clock period, jitter and skew

Learning focus: The latest data arrival must precede capture setup time; earliest arrival must remain valid through hold. Clock uncertainty reduces timing margin.

1. The idea in engineering context

The latest data arrival must precede capture setup time; earliest arrival must remain valid through hold. Clock uncertainty reduces timing margin. This principle belongs within clocking, interfaces and testability. To reason correctly, decide what kind of object each symbol represents: a Boolean truth value, a signed integer, a sample of a waveform, a device threshold, a state bit, or a timed event. An equation may be mathematically valid yet describe the wrong physical or temporal quantity. In a circuit drawing, label all inputs, outputs and control signals with direction and active polarity. If a signal can be unknown, undefined or invalid, describe what the receiving block must do rather than silently treating the signal as zero.

A useful preliminary step is to state the behavior without naming any particular component. For the topic clock period, jitter and skew, write an input-output contract in plain language and translate it to a truth table, transition table, numerical equation or timing diagram as appropriate. The same contract should survive translation into a schematic, a behavioral simulation and an HDL module. If an implementation changes the contract, the change must be documented as a new requirement rather than hidden as a convenience.

2. A checkable example

With a 10 ns period, 1 ns clock-to-Q, 6 ns logic, 1 ns setup and 0.5 ns uncertainty, setup slack is 1.5 ns ignoring skew. Reproduce this calculation or Boolean reasoning from the definitions, showing intermediate bit patterns and units where relevant. When the example uses an idealized value, state explicitly that the numerical values are illustrative teaching inputs, not component specifications. If it refers to a word length, compute the representable range; if it refers to timing, identify the relevant clock domain, edge and uncertainty terms; and if it refers to a voltage, distinguish absolute maximum ratings from guaranteed digital logic levels.

Alternate check. Explain the expected result qualitatively before computing it. A binary carry chain, parity function, or state transition often has an intuitive conserved property: changing one input can affect a particular output but not every unrelated output. Compare the intuitive expectation with the mathematical answer and resolve discrepancies by writing a smaller exhaustive example. This is especially important when signed interpretation, bit ordering or active-low conventions may reverse an apparently obvious answer.

3. Design method and derivation

Memory and width discipline. Record whether the unit reads or writes on the active edge, whether outputs are combinational or registered, and what an address means in bytes or words. The width of intermediate arithmetic can change the computed result even when the mathematical expression looks correct. Where hardware behavior is device-specific, include explicit assumptions and avoid relying on simulator defaults. Test first and last valid addresses and deliberately malformed transactions.

The next step is to make the dependence of output on input explicit. Start with the simplest special case: zero data, inactive enable, reset asserted, or minimum address as appropriate. Then test the opposite boundary, including all-one words, maximum carry, saturated load, or final counter state. For clock period, jitter and skew, list which of these tests are informative and which are irrelevant. Do not automatically assign meaning to a don't-care or illegal combination. If a simplification assumes certain input codes never occur, describe how the enclosing system enforces that assumption.

Verification traceability. Link each requirement to at least one test. Functional cases should include nominal behavior, boundary inputs, reset sequences and conflicting requests; timing claims require separate static timing analysis or measurements. Use a reference calculation that does not duplicate the implementation's structure. Record the simulator version, test seed, expected outputs and observed failures. A passing simulation establishes only the properties exercised under the model.

4. Failure modes and limits

Topic-specific pitfall: Excessive positive skew can improve setup and worsen hold, depending on the launch/capture convention. A reliable engineering write-up names the condition that triggers the failure, the observable symptom and the quickest discriminating test. For a functional bug, compare expected and actual truth-table rows; for a timing bug, inspect waveform edges and clock assumptions; for a numeric bug, inspect sign extension and intermediate widths; and for an interface bug, check whether validity and acknowledgement share the same interpretation at each endpoint.

Unit-level model boundary: A two-flop synchronizer reduces metastability risk but does not make multi-bit asynchronous transfers coherent. Avoid extrapolating an ideal gate model into a claim about any particular commercial part. Robustness also requires considering reset entry, temperature-dependent device performance and asynchronous external disturbances whenever they are relevant. If a measured device disagrees with a model, first verify the input stimulus, measurement bandwidth and grounding before declaring the underlying logic theory incorrect.

5. Worked design workflow

1. Specify: write a sentence that defines each input, output and its width; resolve any ambiguous invalid or simultaneous input behavior.

2. Model: select a Boolean expression, transition relation or time equation that captures the defined behavior and state all assumptions.

3. Derive: compute the result for the particular illustrative case above. If there is arithmetic, keep bit widths explicit through every intermediate operation.

4. Cross-check: compare against an independently enumerated case or a direct formula. Document discrepancies rather than adjusting the expected answer to match the implementation.

5. Implement: map the model to gates or synthesizable RTL, leaving enough information to identify clocking, reset and active polarities.

6. Verify: test boundaries and one deliberate fault injection, then record whether the result is logical, simulated, measured or formally proven.

This workflow is intentionally stricter than drawing a plausible diagram. An executable calculator can confirm arithmetic while missing an incorrect interpretation of its inputs. Conversely, a timing waveform can look convincing even if the specification omitted a simultaneous request. A successful solution must connect intent, derivation and independent observation.

6. Laboratory and simulation protocol

Investigation: Prepare separate max-delay and min-delay timing checks. Construct a small input matrix containing at least one nominal case, a lower boundary, an upper boundary and a deliberately ambiguous or invalid stimulus. Before running a browser model, write your predicted output and the rule that supports it. Run the experiment, record the output and compare. If the model disagrees with your prediction, determine whether the error is in your rule, your convention, or the model. Explicitly distinguish calculated values from observed electrical measurements; the provided browser apps are not instruments connected to hardware.

Extensions. Repeat the test with an input changed by one bit or one clock cycle. If the result is unchanged, explain which invariance made that possible. If the result changes, identify the exact dependency path. Next ask whether this exercise would still work with a real gate driving several receivers, a different supply voltage, or a clock with uncertainty. That question may require a data sheet, timing analysis or physical measurement beyond the ideal simulation.

7. Guided exercises

1. Derive and explain. Starting from the definition behind clock period, jitter and skew, construct the smallest nontrivial truth table, bit pattern, timing diagram or state-transition example. Label all relevant conventions. Provide an independent cross-check.

2. Boundary case. Modify the worked example so that one parameter is at its legal minimum and another at its legal maximum. Recompute the expected result and explain whether the nominal assumption still holds.

3. Find the error. Analyze this claim: “Excessive positive skew can improve setup and worsen hold, depending on the launch/capture convention.” Identify a concrete input condition that reveals the problem, describe the output symptom and propose a correction or safety guard.

4. Design choice. Compare two implementations of the lesson's function: a direct gate-level representation and a modular block with explicit interface signals. State their likely advantages in clarity, area, timing or testability without assuming a universal winner.

5. Verification. Write five test vectors (including a boundary and invalid input), expected results and a single assertion or invariant that should hold across the set. Explain how a false-positive test could occur.

8. Reflection and further study

The central question of Clock period, jitter and skew is not whether an expression looks familiar, but whether a particular result follows from a complete set of stated assumptions. Recheck the significance of each bit and event, the boundary conditions and the consequences of implementing the abstraction in physical hardware. In design reviews, a clearly documented failed assumption is more valuable than a visually polished schematic with hidden undefined behavior. Before moving on, write a three-sentence summary: what this mechanism guarantees, what it does not guarantee, and the simplest independent test that would reveal a mistake.

§7.2 Asynchronous inputs and synchronizers

Unit 7, Lesson 2: Asynchronous inputs and synchronizers

Learning focus: Two-stage synchronization reduces risk of metastability reaching synchronous logic, but does not eliminate the possibility or guarantee pulse capture.

1. The idea in engineering context

Two-stage synchronization reduces risk of metastability reaching synchronous logic, but does not eliminate the possibility or guarantee pulse capture. This principle belongs within clocking, interfaces and testability. To reason correctly, decide what kind of object each symbol represents: a Boolean truth value, a signed integer, a sample of a waveform, a device threshold, a state bit, or a timed event. An equation may be mathematically valid yet describe the wrong physical or temporal quantity. In a circuit drawing, label all inputs, outputs and control signals with direction and active polarity. If a signal can be unknown, undefined or invalid, describe what the receiving block must do rather than silently treating the signal as zero.

A useful preliminary step is to state the behavior without naming any particular component. For the topic asynchronous inputs and synchronizers, write an input-output contract in plain language and translate it to a truth table, transition table, numerical equation or timing diagram as appropriate. The same contract should survive translation into a schematic, a behavioral simulation and an HDL module. If an implementation changes the contract, the change must be documented as a new requirement rather than hidden as a convenience.

2. A checkable example

A 2 ns pulse entering a 100 MHz domain can disappear entirely between 10 ns sample edges. Reproduce this calculation or Boolean reasoning from the definitions, showing intermediate bit patterns and units where relevant. When the example uses an idealized value, state explicitly that the numerical values are illustrative teaching inputs, not component specifications. If it refers to a word length, compute the representable range; if it refers to timing, identify the relevant clock domain, edge and uncertainty terms; and if it refers to a voltage, distinguish absolute maximum ratings from guaranteed digital logic levels.

Alternate check. Explain the expected result qualitatively before computing it. A binary carry chain, parity function, or state transition often has an intuitive conserved property: changing one input can affect a particular output but not every unrelated output. Compare the intuitive expectation with the mathematical answer and resolve discrepancies by writing a smaller exhaustive example. This is especially important when signed interpretation, bit ordering or active-low conventions may reverse an apparently obvious answer.

3. Design method and derivation

Memory and width discipline. Record whether the unit reads or writes on the active edge, whether outputs are combinational or registered, and what an address means in bytes or words. The width of intermediate arithmetic can change the computed result even when the mathematical expression looks correct. Where hardware behavior is device-specific, include explicit assumptions and avoid relying on simulator defaults. Test first and last valid addresses and deliberately malformed transactions.

The next step is to make the dependence of output on input explicit. Start with the simplest special case: zero data, inactive enable, reset asserted, or minimum address as appropriate. Then test the opposite boundary, including all-one words, maximum carry, saturated load, or final counter state. For asynchronous inputs and synchronizers, list which of these tests are informative and which are irrelevant. Do not automatically assign meaning to a don't-care or illegal combination. If a simplification assumes certain input codes never occur, describe how the enclosing system enforces that assumption.

Verification traceability. Link each requirement to at least one test. Functional cases should include nominal behavior, boundary inputs, reset sequences and conflicting requests; timing claims require separate static timing analysis or measurements. Use a reference calculation that does not duplicate the implementation's structure. Record the simulator version, test seed, expected outputs and observed failures. A passing simulation establishes only the properties exercised under the model.

4. Failure modes and limits

Topic-specific pitfall: Synchronizing each bit of a changing data bus separately does not preserve word coherence. A reliable engineering write-up names the condition that triggers the failure, the observable symptom and the quickest discriminating test. For a functional bug, compare expected and actual truth-table rows; for a timing bug, inspect waveform edges and clock assumptions; for a numeric bug, inspect sign extension and intermediate widths; and for an interface bug, check whether validity and acknowledgement share the same interpretation at each endpoint.

Unit-level model boundary: A two-flop synchronizer reduces metastability risk but does not make multi-bit asynchronous transfers coherent. Avoid extrapolating an ideal gate model into a claim about any particular commercial part. Robustness also requires considering reset entry, temperature-dependent device performance and asynchronous external disturbances whenever they are relevant. If a measured device disagrees with a model, first verify the input stimulus, measurement bandwidth and grounding before declaring the underlying logic theory incorrect.

5. Worked design workflow

1. Specify: write a sentence that defines each input, output and its width; resolve any ambiguous invalid or simultaneous input behavior.

2. Model: select a Boolean expression, transition relation or time equation that captures the defined behavior and state all assumptions.

3. Derive: compute the result for the particular illustrative case above. If there is arithmetic, keep bit widths explicit through every intermediate operation.

4. Cross-check: compare against an independently enumerated case or a direct formula. Document discrepancies rather than adjusting the expected answer to match the implementation.

5. Implement: map the model to gates or synthesizable RTL, leaving enough information to identify clocking, reset and active polarities.

6. Verify: test boundaries and one deliberate fault injection, then record whether the result is logical, simulated, measured or formally proven.

This workflow is intentionally stricter than drawing a plausible diagram. An executable calculator can confirm arithmetic while missing an incorrect interpretation of its inputs. Conversely, a timing waveform can look convincing even if the specification omitted a simultaneous request. A successful solution must connect intent, derivation and independent observation.

6. Laboratory and simulation protocol

Investigation: Choose a toggle, handshake or FIFO architecture for three crossing cases. Construct a small input matrix containing at least one nominal case, a lower boundary, an upper boundary and a deliberately ambiguous or invalid stimulus. Before running a browser model, write your predicted output and the rule that supports it. Run the experiment, record the output and compare. If the model disagrees with your prediction, determine whether the error is in your rule, your convention, or the model. Explicitly distinguish calculated values from observed electrical measurements; the provided browser apps are not instruments connected to hardware.

Extensions. Repeat the test with an input changed by one bit or one clock cycle. If the result is unchanged, explain which invariance made that possible. If the result changes, identify the exact dependency path. Next ask whether this exercise would still work with a real gate driving several receivers, a different supply voltage, or a clock with uncertainty. That question may require a data sheet, timing analysis or physical measurement beyond the ideal simulation.

7. Guided exercises

1. Derive and explain. Starting from the definition behind asynchronous inputs and synchronizers, construct the smallest nontrivial truth table, bit pattern, timing diagram or state-transition example. Label all relevant conventions. Provide an independent cross-check.

2. Boundary case. Modify the worked example so that one parameter is at its legal minimum and another at its legal maximum. Recompute the expected result and explain whether the nominal assumption still holds.

3. Find the error. Analyze this claim: “Synchronizing each bit of a changing data bus separately does not preserve word coherence.” Identify a concrete input condition that reveals the problem, describe the output symptom and propose a correction or safety guard.

4. Design choice. Compare two implementations of the lesson's function: a direct gate-level representation and a modular block with explicit interface signals. State their likely advantages in clarity, area, timing or testability without assuming a universal winner.

5. Verification. Write five test vectors (including a boundary and invalid input), expected results and a single assertion or invariant that should hold across the set. Explain how a false-positive test could occur.

8. Reflection and further study

The central question of Asynchronous inputs and synchronizers is not whether an expression looks familiar, but whether a particular result follows from a complete set of stated assumptions. Recheck the significance of each bit and event, the boundary conditions and the consequences of implementing the abstraction in physical hardware. In design reviews, a clearly documented failed assumption is more valuable than a visually polished schematic with hidden undefined behavior. Before moving on, write a three-sentence summary: what this mechanism guarantees, what it does not guarantee, and the simplest independent test that would reveal a mistake.

§7.3 Switch bounce and debouncing

Unit 7, Lesson 3: Switch bounce and debouncing

Learning focus: Mechanical contacts can chatter for milliseconds, generating many logical transitions. Debouncing requires a time policy and may add response latency.

1. The idea in engineering context

Mechanical contacts can chatter for milliseconds, generating many logical transitions. Debouncing requires a time policy and may add response latency. This principle belongs within clocking, interfaces and testability. To reason correctly, decide what kind of object each symbol represents: a Boolean truth value, a signed integer, a sample of a waveform, a device threshold, a state bit, or a timed event. An equation may be mathematically valid yet describe the wrong physical or temporal quantity. In a circuit drawing, label all inputs, outputs and control signals with direction and active polarity. If a signal can be unknown, undefined or invalid, describe what the receiving block must do rather than silently treating the signal as zero.

A useful preliminary step is to state the behavior without naming any particular component. For the topic switch bounce and debouncing, write an input-output contract in plain language and translate it to a truth table, transition table, numerical equation or timing diagram as appropriate. The same contract should survive translation into a schematic, a behavioral simulation and an HDL module. If an implementation changes the contract, the change must be documented as a new requirement rather than hidden as a convenience.

2. A checkable example

A 1 ms stable-time filter sampled every 0.1 ms requires ten consecutive stable samples before accepting a new level. Reproduce this calculation or Boolean reasoning from the definitions, showing intermediate bit patterns and units where relevant. When the example uses an idealized value, state explicitly that the numerical values are illustrative teaching inputs, not component specifications. If it refers to a word length, compute the representable range; if it refers to timing, identify the relevant clock domain, edge and uncertainty terms; and if it refers to a voltage, distinguish absolute maximum ratings from guaranteed digital logic levels.

Alternate check. Explain the expected result qualitatively before computing it. A binary carry chain, parity function, or state transition often has an intuitive conserved property: changing one input can affect a particular output but not every unrelated output. Compare the intuitive expectation with the mathematical answer and resolve discrepancies by writing a smaller exhaustive example. This is especially important when signed interpretation, bit ordering or active-low conventions may reverse an apparently obvious answer.

3. Design method and derivation

Memory and width discipline. Record whether the unit reads or writes on the active edge, whether outputs are combinational or registered, and what an address means in bytes or words. The width of intermediate arithmetic can change the computed result even when the mathematical expression looks correct. Where hardware behavior is device-specific, include explicit assumptions and avoid relying on simulator defaults. Test first and last valid addresses and deliberately malformed transactions.

The next step is to make the dependence of output on input explicit. Start with the simplest special case: zero data, inactive enable, reset asserted, or minimum address as appropriate. Then test the opposite boundary, including all-one words, maximum carry, saturated load, or final counter state. For switch bounce and debouncing, list which of these tests are informative and which are irrelevant. Do not automatically assign meaning to a don't-care or illegal combination. If a simplification assumes certain input codes never occur, describe how the enclosing system enforces that assumption.

Verification traceability. Link each requirement to at least one test. Functional cases should include nominal behavior, boundary inputs, reset sequences and conflicting requests; timing claims require separate static timing analysis or measurements. Use a reference calculation that does not duplicate the implementation's structure. Record the simulator version, test seed, expected outputs and observed failures. A passing simulation establishes only the properties exercised under the model.

4. Failure modes and limits

Topic-specific pitfall: A fast sampling loop can make bounce appear worse because it sees additional edges. A reliable engineering write-up names the condition that triggers the failure, the observable symptom and the quickest discriminating test. For a functional bug, compare expected and actual truth-table rows; for a timing bug, inspect waveform edges and clock assumptions; for a numeric bug, inspect sign extension and intermediate widths; and for an interface bug, check whether validity and acknowledgement share the same interpretation at each endpoint.

Unit-level model boundary: A two-flop synchronizer reduces metastability risk but does not make multi-bit asynchronous transfers coherent. Avoid extrapolating an ideal gate model into a claim about any particular commercial part. Robustness also requires considering reset entry, temperature-dependent device performance and asynchronous external disturbances whenever they are relevant. If a measured device disagrees with a model, first verify the input stimulus, measurement bandwidth and grounding before declaring the underlying logic theory incorrect.

5. Worked design workflow

1. Specify: write a sentence that defines each input, output and its width; resolve any ambiguous invalid or simultaneous input behavior.

2. Model: select a Boolean expression, transition relation or time equation that captures the defined behavior and state all assumptions.

3. Derive: compute the result for the particular illustrative case above. If there is arithmetic, keep bit widths explicit through every intermediate operation.

4. Cross-check: compare against an independently enumerated case or a direct formula. Document discrepancies rather than adjusting the expected answer to match the implementation.

5. Implement: map the model to gates or synthesizable RTL, leaving enough information to identify clocking, reset and active polarities.

6. Verify: test boundaries and one deliberate fault injection, then record whether the result is logical, simulated, measured or formally proven.

This workflow is intentionally stricter than drawing a plausible diagram. An executable calculator can confirm arithmetic while missing an incorrect interpretation of its inputs. Conversely, a timing waveform can look convincing even if the specification omitted a simultaneous request. A successful solution must connect intent, derivation and independent observation.

6. Laboratory and simulation protocol

Investigation: Design a debouncer that distinguishes short spikes from intentional presses. Construct a small input matrix containing at least one nominal case, a lower boundary, an upper boundary and a deliberately ambiguous or invalid stimulus. Before running a browser model, write your predicted output and the rule that supports it. Run the experiment, record the output and compare. If the model disagrees with your prediction, determine whether the error is in your rule, your convention, or the model. Explicitly distinguish calculated values from observed electrical measurements; the provided browser apps are not instruments connected to hardware.

Extensions. Repeat the test with an input changed by one bit or one clock cycle. If the result is unchanged, explain which invariance made that possible. If the result changes, identify the exact dependency path. Next ask whether this exercise would still work with a real gate driving several receivers, a different supply voltage, or a clock with uncertainty. That question may require a data sheet, timing analysis or physical measurement beyond the ideal simulation.

7. Guided exercises

1. Derive and explain. Starting from the definition behind switch bounce and debouncing, construct the smallest nontrivial truth table, bit pattern, timing diagram or state-transition example. Label all relevant conventions. Provide an independent cross-check.

2. Boundary case. Modify the worked example so that one parameter is at its legal minimum and another at its legal maximum. Recompute the expected result and explain whether the nominal assumption still holds.

3. Find the error. Analyze this claim: “A fast sampling loop can make bounce appear worse because it sees additional edges.” Identify a concrete input condition that reveals the problem, describe the output symptom and propose a correction or safety guard.

4. Design choice. Compare two implementations of the lesson's function: a direct gate-level representation and a modular block with explicit interface signals. State their likely advantages in clarity, area, timing or testability without assuming a universal winner.

5. Verification. Write five test vectors (including a boundary and invalid input), expected results and a single assertion or invariant that should hold across the set. Explain how a false-positive test could occur.

8. Reflection and further study

The central question of Switch bounce and debouncing is not whether an expression looks familiar, but whether a particular result follows from a complete set of stated assumptions. Recheck the significance of each bit and event, the boundary conditions and the consequences of implementing the abstraction in physical hardware. In design reviews, a clearly documented failed assumption is more valuable than a visually polished schematic with hidden undefined behavior. Before moving on, write a three-sentence summary: what this mechanism guarantees, what it does not guarantee, and the simplest independent test that would reveal a mistake.

§7.4 Logic analyzers, boundary conditions and test

Unit 7, Lesson 4: Logic analyzers, boundary conditions and test

Learning focus: A logic analyzer reveals digital timing, but sampling and threshold selection can hide narrow pulses and analog ringing. Test vectors should include boundary and simultaneous conditions.

1. The idea in engineering context

A logic analyzer reveals digital timing, but sampling and threshold selection can hide narrow pulses and analog ringing. Test vectors should include boundary and simultaneous conditions. This principle belongs within clocking, interfaces and testability. To reason correctly, decide what kind of object each symbol represents: a Boolean truth value, a signed integer, a sample of a waveform, a device threshold, a state bit, or a timed event. An equation may be mathematically valid yet describe the wrong physical or temporal quantity. In a circuit drawing, label all inputs, outputs and control signals with direction and active polarity. If a signal can be unknown, undefined or invalid, describe what the receiving block must do rather than silently treating the signal as zero.

A useful preliminary step is to state the behavior without naming any particular component. For the topic logic analyzers, boundary conditions and test, write an input-output contract in plain language and translate it to a truth table, transition table, numerical equation or timing diagram as appropriate. The same contract should survive translation into a schematic, a behavioral simulation and an HDL module. If an implementation changes the contract, the change must be documented as a new requirement rather than hidden as a convenience.

2. A checkable example

At 20 MS/s, samples arrive every 50 ns; a 10 ns glitch may go unobserved. Reproduce this calculation or Boolean reasoning from the definitions, showing intermediate bit patterns and units where relevant. When the example uses an idealized value, state explicitly that the numerical values are illustrative teaching inputs, not component specifications. If it refers to a word length, compute the representable range; if it refers to timing, identify the relevant clock domain, edge and uncertainty terms; and if it refers to a voltage, distinguish absolute maximum ratings from guaranteed digital logic levels.

Alternate check. Explain the expected result qualitatively before computing it. A binary carry chain, parity function, or state transition often has an intuitive conserved property: changing one input can affect a particular output but not every unrelated output. Compare the intuitive expectation with the mathematical answer and resolve discrepancies by writing a smaller exhaustive example. This is especially important when signed interpretation, bit ordering or active-low conventions may reverse an apparently obvious answer.

3. Design method and derivation

Memory and width discipline. Record whether the unit reads or writes on the active edge, whether outputs are combinational or registered, and what an address means in bytes or words. The width of intermediate arithmetic can change the computed result even when the mathematical expression looks correct. Where hardware behavior is device-specific, include explicit assumptions and avoid relying on simulator defaults. Test first and last valid addresses and deliberately malformed transactions.

The next step is to make the dependence of output on input explicit. Start with the simplest special case: zero data, inactive enable, reset asserted, or minimum address as appropriate. Then test the opposite boundary, including all-one words, maximum carry, saturated load, or final counter state. For logic analyzers, boundary conditions and test, list which of these tests are informative and which are irrelevant. Do not automatically assign meaning to a don't-care or illegal combination. If a simplification assumes certain input codes never occur, describe how the enclosing system enforces that assumption.

Verification traceability. Link each requirement to at least one test. Functional cases should include nominal behavior, boundary inputs, reset sequences and conflicting requests; timing claims require separate static timing analysis or measurements. Use a reference calculation that does not duplicate the implementation's structure. Record the simulator version, test seed, expected outputs and observed failures. A passing simulation establishes only the properties exercised under the model.

4. Failure modes and limits

Topic-specific pitfall: A clean digital trace cannot by itself establish voltage overshoot compliance. A reliable engineering write-up names the condition that triggers the failure, the observable symptom and the quickest discriminating test. For a functional bug, compare expected and actual truth-table rows; for a timing bug, inspect waveform edges and clock assumptions; for a numeric bug, inspect sign extension and intermediate widths; and for an interface bug, check whether validity and acknowledgement share the same interpretation at each endpoint.

Unit-level model boundary: A two-flop synchronizer reduces metastability risk but does not make multi-bit asynchronous transfers coherent. Avoid extrapolating an ideal gate model into a claim about any particular commercial part. Robustness also requires considering reset entry, temperature-dependent device performance and asynchronous external disturbances whenever they are relevant. If a measured device disagrees with a model, first verify the input stimulus, measurement bandwidth and grounding before declaring the underlying logic theory incorrect.

5. Worked design workflow

1. Specify: write a sentence that defines each input, output and its width; resolve any ambiguous invalid or simultaneous input behavior.

2. Model: select a Boolean expression, transition relation or time equation that captures the defined behavior and state all assumptions.

3. Derive: compute the result for the particular illustrative case above. If there is arithmetic, keep bit widths explicit through every intermediate operation.

4. Cross-check: compare against an independently enumerated case or a direct formula. Document discrepancies rather than adjusting the expected answer to match the implementation.

5. Implement: map the model to gates or synthesizable RTL, leaving enough information to identify clocking, reset and active polarities.

6. Verify: test boundaries and one deliberate fault injection, then record whether the result is logical, simulated, measured or formally proven.

This workflow is intentionally stricter than drawing a plausible diagram. An executable calculator can confirm arithmetic while missing an incorrect interpretation of its inputs. Conversely, a timing waveform can look convincing even if the specification omitted a simultaneous request. A successful solution must connect intent, derivation and independent observation.

6. Laboratory and simulation protocol

Investigation: Construct a reproducible bench plan with oscilloscope, logic analyzer and reference clock. Construct a small input matrix containing at least one nominal case, a lower boundary, an upper boundary and a deliberately ambiguous or invalid stimulus. Before running a browser model, write your predicted output and the rule that supports it. Run the experiment, record the output and compare. If the model disagrees with your prediction, determine whether the error is in your rule, your convention, or the model. Explicitly distinguish calculated values from observed electrical measurements; the provided browser apps are not instruments connected to hardware.

Extensions. Repeat the test with an input changed by one bit or one clock cycle. If the result is unchanged, explain which invariance made that possible. If the result changes, identify the exact dependency path. Next ask whether this exercise would still work with a real gate driving several receivers, a different supply voltage, or a clock with uncertainty. That question may require a data sheet, timing analysis or physical measurement beyond the ideal simulation.

7. Guided exercises

1. Derive and explain. Starting from the definition behind logic analyzers, boundary conditions and test, construct the smallest nontrivial truth table, bit pattern, timing diagram or state-transition example. Label all relevant conventions. Provide an independent cross-check.

2. Boundary case. Modify the worked example so that one parameter is at its legal minimum and another at its legal maximum. Recompute the expected result and explain whether the nominal assumption still holds.

3. Find the error. Analyze this claim: “A clean digital trace cannot by itself establish voltage overshoot compliance.” Identify a concrete input condition that reveals the problem, describe the output symptom and propose a correction or safety guard.

4. Design choice. Compare two implementations of the lesson's function: a direct gate-level representation and a modular block with explicit interface signals. State their likely advantages in clarity, area, timing or testability without assuming a universal winner.

5. Verification. Write five test vectors (including a boundary and invalid input), expected results and a single assertion or invariant that should hold across the set. Explain how a false-positive test could occur.

8. Reflection and further study

The central question of Logic analyzers, boundary conditions and test is not whether an expression looks familiar, but whether a particular result follows from a complete set of stated assumptions. Recheck the significance of each bit and event, the boundary conditions and the consequences of implementing the abstraction in physical hardware. In design reviews, a clearly documented failed assumption is more valuable than a visually polished schematic with hidden undefined behavior. Before moving on, write a three-sentence summary: what this mechanism guarantees, what it does not guarantee, and the simplest independent test that would reveal a mistake.

§7.5 Fault models and design-for-test

Unit 7, Lesson 5: Fault models and design-for-test

Learning focus: Stuck-at faults, bridging faults and timing faults are abstractions for testing. Scan chains increase controllability and observability of sequential logic.

1. The idea in engineering context

Stuck-at faults, bridging faults and timing faults are abstractions for testing. Scan chains increase controllability and observability of sequential logic. This principle belongs within clocking, interfaces and testability. To reason correctly, decide what kind of object each symbol represents: a Boolean truth value, a signed integer, a sample of a waveform, a device threshold, a state bit, or a timed event. An equation may be mathematically valid yet describe the wrong physical or temporal quantity. In a circuit drawing, label all inputs, outputs and control signals with direction and active polarity. If a signal can be unknown, undefined or invalid, describe what the receiving block must do rather than silently treating the signal as zero.

A useful preliminary step is to state the behavior without naming any particular component. For the topic fault models and design-for-test, write an input-output contract in plain language and translate it to a truth table, transition table, numerical equation or timing diagram as appropriate. The same contract should survive translation into a schematic, a behavioral simulation and an HDL module. If an implementation changes the contract, the change must be documented as a new requirement rather than hidden as a convenience.

2. A checkable example

To detect a stuck-at-0 fault on a node, stimulate a case that should set that node to 1 and propagate the effect to an observable output. Reproduce this calculation or Boolean reasoning from the definitions, showing intermediate bit patterns and units where relevant. When the example uses an idealized value, state explicitly that the numerical values are illustrative teaching inputs, not component specifications. If it refers to a word length, compute the representable range; if it refers to timing, identify the relevant clock domain, edge and uncertainty terms; and if it refers to a voltage, distinguish absolute maximum ratings from guaranteed digital logic levels.

Alternate check. Explain the expected result qualitatively before computing it. A binary carry chain, parity function, or state transition often has an intuitive conserved property: changing one input can affect a particular output but not every unrelated output. Compare the intuitive expectation with the mathematical answer and resolve discrepancies by writing a smaller exhaustive example. This is especially important when signed interpretation, bit ordering or active-low conventions may reverse an apparently obvious answer.

3. Design method and derivation

Memory and width discipline. Record whether the unit reads or writes on the active edge, whether outputs are combinational or registered, and what an address means in bytes or words. The width of intermediate arithmetic can change the computed result even when the mathematical expression looks correct. Where hardware behavior is device-specific, include explicit assumptions and avoid relying on simulator defaults. Test first and last valid addresses and deliberately malformed transactions.

The next step is to make the dependence of output on input explicit. Start with the simplest special case: zero data, inactive enable, reset asserted, or minimum address as appropriate. Then test the opposite boundary, including all-one words, maximum carry, saturated load, or final counter state. For fault models and design-for-test, list which of these tests are informative and which are irrelevant. Do not automatically assign meaning to a don't-care or illegal combination. If a simplification assumes certain input codes never occur, describe how the enclosing system enforces that assumption.

Verification traceability. Link each requirement to at least one test. Functional cases should include nominal behavior, boundary inputs, reset sequences and conflicting requests; timing claims require separate static timing analysis or measurements. Use a reference calculation that does not duplicate the implementation's structure. Record the simulator version, test seed, expected outputs and observed failures. A passing simulation establishes only the properties exercised under the model.

4. Failure modes and limits

Topic-specific pitfall: A fault can be structurally present but unobservable under an incomplete test suite. A reliable engineering write-up names the condition that triggers the failure, the observable symptom and the quickest discriminating test. For a functional bug, compare expected and actual truth-table rows; for a timing bug, inspect waveform edges and clock assumptions; for a numeric bug, inspect sign extension and intermediate widths; and for an interface bug, check whether validity and acknowledgement share the same interpretation at each endpoint.

Unit-level model boundary: A two-flop synchronizer reduces metastability risk but does not make multi-bit asynchronous transfers coherent. Avoid extrapolating an ideal gate model into a claim about any particular commercial part. Robustness also requires considering reset entry, temperature-dependent device performance and asynchronous external disturbances whenever they are relevant. If a measured device disagrees with a model, first verify the input stimulus, measurement bandwidth and grounding before declaring the underlying logic theory incorrect.

5. Worked design workflow

1. Specify: write a sentence that defines each input, output and its width; resolve any ambiguous invalid or simultaneous input behavior.

2. Model: select a Boolean expression, transition relation or time equation that captures the defined behavior and state all assumptions.

3. Derive: compute the result for the particular illustrative case above. If there is arithmetic, keep bit widths explicit through every intermediate operation.

4. Cross-check: compare against an independently enumerated case or a direct formula. Document discrepancies rather than adjusting the expected answer to match the implementation.

5. Implement: map the model to gates or synthesizable RTL, leaving enough information to identify clocking, reset and active polarities.

6. Verify: test boundaries and one deliberate fault injection, then record whether the result is logical, simulated, measured or formally proven.

This workflow is intentionally stricter than drawing a plausible diagram. An executable calculator can confirm arithmetic while missing an incorrect interpretation of its inputs. Conversely, a timing waveform can look convincing even if the specification omitted a simultaneous request. A successful solution must connect intent, derivation and independent observation.

6. Laboratory and simulation protocol

Investigation: Write vectors for stuck-at faults in a two-input AND gate and explain detection. Construct a small input matrix containing at least one nominal case, a lower boundary, an upper boundary and a deliberately ambiguous or invalid stimulus. Before running a browser model, write your predicted output and the rule that supports it. Run the experiment, record the output and compare. If the model disagrees with your prediction, determine whether the error is in your rule, your convention, or the model. Explicitly distinguish calculated values from observed electrical measurements; the provided browser apps are not instruments connected to hardware.

Extensions. Repeat the test with an input changed by one bit or one clock cycle. If the result is unchanged, explain which invariance made that possible. If the result changes, identify the exact dependency path. Next ask whether this exercise would still work with a real gate driving several receivers, a different supply voltage, or a clock with uncertainty. That question may require a data sheet, timing analysis or physical measurement beyond the ideal simulation.

7. Guided exercises

1. Derive and explain. Starting from the definition behind fault models and design-for-test, construct the smallest nontrivial truth table, bit pattern, timing diagram or state-transition example. Label all relevant conventions. Provide an independent cross-check.

2. Boundary case. Modify the worked example so that one parameter is at its legal minimum and another at its legal maximum. Recompute the expected result and explain whether the nominal assumption still holds.

3. Find the error. Analyze this claim: “A fault can be structurally present but unobservable under an incomplete test suite.” Identify a concrete input condition that reveals the problem, describe the output symptom and propose a correction or safety guard.

4. Design choice. Compare two implementations of the lesson's function: a direct gate-level representation and a modular block with explicit interface signals. State their likely advantages in clarity, area, timing or testability without assuming a universal winner.

5. Verification. Write five test vectors (including a boundary and invalid input), expected results and a single assertion or invariant that should hold across the set. Explain how a false-positive test could occur.

8. Reflection and further study

The central question of Fault models and design-for-test is not whether an expression looks familiar, but whether a particular result follows from a complete set of stated assumptions. Recheck the significance of each bit and event, the boundary conditions and the consequences of implementing the abstraction in physical hardware. In design reviews, a clearly documented failed assumption is more valuable than a visually polished schematic with hidden undefined behavior. Before moving on, write a three-sentence summary: what this mechanism guarantees, what it does not guarantee, and the simplest independent test that would reveal a mistake.