Latches, Flip-Flops & Multivibrator Timing Circuits

1. The Fundamental Bistable Circuit Principle

While combinational circuits produce outputs that depend strictly on current inputs, sequential circuits incorporate memory elements whose outputs depend on both current inputs and the past sequence of states. The most primitive electronic memory cell is the bistable multivibrator, formed by cross-coupling two inverting stages with positive feedback ($A_v > 1$):

The circuit possesses two stable equilibrium states: State 1 ($Q=1, \bar{Q}=0$, "SET") and State 2 ($Q=0, \bar{Q}=1$, "RESET"). The intermediate state where both inverters operate in their linear amplification region ($V_{\text{in}} = V_{\text{out}} \approx V_{DD}/2$) is metastable; infinitesimal thermal noise forces the cell to regenerate into one of the two stable binary states.

2. Active-HIGH NOR Latch

Constructed by cross-coupling two 2-input NOR gates with inputs $S$ (Set) and $R$ (Reset):

• $S=0, R=0$: Hold / Memory State ($Q_{n+1} = Q_n$). Latches the previous bit indefinitely.
• $S=1, R=0$: Set State ($Q_{n+1} = 1, \bar{Q}_{n+1} = 0$).
• $S=0, R=1$: Reset State ($Q_{n+1} = 0, \bar{Q}_{n+1} = 1$).
• $S=1, R=1$: Forbidden / Invalid State. Forces both outputs to $0$ ($Q = \bar{Q} = 0$), violating complementarity. If both inputs return simultaneously to $0$, race conditions lead to unpredictable metastable collapse.

3. Active-LOW NAND Latch

Constructed by cross-coupling two 2-input NAND gates with active-LOW inputs $\bar{S}$ and $\bar{R}$:

• $\bar{S}=1, \bar{R}=1$: Hold State.
• $\bar{S}=0, \bar{R}=1$: Set State ($Q=1$).
• $\bar{S}=1, \bar{R}=0$: Reset State ($Q=0$).
• $\bar{S}=0, \bar{R}=0$: Forbidden State ($Q = \bar{Q} = 1$).

1. Clocked SR Latch

To synchronize state transitions with a central clock signal ($CLK$), two steering NAND gates precede the basic NAND latch:

• When $CLK = 0$: $S^* = R^* = 1$. The latch remains frozen in its hold state regardless of $S$ and $R$.
• When $CLK = 1$: $S^* = \bar{S}$ and $R^* = \bar{R}$. The latch responds directly to $S$ and $R$ inputs.

2. The Transparent D Latch

To eliminate the forbidden $S=R=1$ hazard, an inverter is placed between the inputs ($R = \bar{S}$), creating the single-input Data or D Latch ($S = D, R = \bar{D}$):

• Transparent Mode ($CLK = 1$): The output $Q$ tracks input $D$ continuously in real time with minimal gate delay. Any noise or glitches on $D$ propagate directly to $Q$.
• Latched Mode ($CLK = 0$): The output $Q$ freezes, holding the value present at $D$ at the instant the clock fell.

1. Edge-Triggering vs Level-Sensitivity

A latch is level-sensitive: it responds continuously as long as the clock enable remains active. In contrast, an edge-triggered flip-flop samples its input and changes state only during an infinitesimal transition edge of the clock signal—either the positive (rising) edge ($0 \to 1$) or the negative (falling) edge ($1 \to 0$).

2. Master-Slave Architecture

A classic edge-triggered flip-flop cascades two clocked latches in series controlled by complementary clock phases:

1. Master Latch: Enabled when $CLK = 1$. Samples data input $D$ while the slave is disabled ($\overline{CLK} = 0$). Output $Q_M$ tracks $D$, but external output $Q$ remains isolated.
2. Slave Latch: Enabled when $CLK$ transitions from $1 \to 0$ ($\overline{CLK} \to 1$). The master latch instantly freezes, and the slave copies the frozen state $Q_M$ to the external output $Q$.

Because the master and slave are never enabled simultaneously, data cannot ripple through both stages in a single clock cycle, completely severing feedthrough loops in shift registers and counters.

3. Dynamic Timing Parameters: Setup Time & Hold Time

Reliable digital state capture requires strict adherence to dynamic timing windows:

• Setup Time ($t_{su}$): The minimum duration that the data input $D$ must remain stable before the active clock edge arrives. Typically $1 - 5\text{ ns}$ (down to tens of picoseconds in deep submicron CMOS).
• Hold Time ($t_h$): The minimum duration that the data input $D$ must remain stable after the active clock edge has transitioned.
• Propagation Delay ($t_{pd} = t_{CLK \to Q}$): The time delay between the active clock edge and the appearance of the new valid state at output $Q$.
• Metastability Hazard: If input $D$ transitions within the forbidden setup/hold aperture ($t_{su} + t_h$), internal regenerative feedback can hang in an indeterminate analog voltage state for an unbounded duration before collapsing randomly to 0 or 1, causing catastrophic hardware crashes.

1. The Race-Around Condition Hazard

In a level-triggered JK latch with inputs $J = K = 1$, the output toggles ($Q \to \bar{Q}$). If the clock pulse width $t_w$ is longer than the propagation delay of the flip-flop ($t_{pd}$):

the newly toggled output will feed back to the input gates while the clock is still HIGH, causing the output to toggle repeatedly back and forth ("race around") throughout the pulse duration $t_w$. The final state of $Q$ when the clock falls is completely unpredictable.

Race-Around Elimination Methods:

1. Narrow clock pulses ($t_w < t_{pd}$, difficult to guarantee across temperature and process variations).
2. Edge-Triggered Design: State transitions occur only during clock edges ($\sim 1\text{ ns}$).
3. Master-Slave JK Flip-Flop: The master isolates inputs while the slave updates outputs.

2. Truth Table & Characteristic Equation of the JK Flip-Flop

From the K-map of next-state $Q_{n+1}$, the Characteristic Equation is:

3. The Toggle (T) Flip-Flop

Formed by tying the $J$ and $K$ inputs together ($J = K = T$):

• When $T = 0$: $Q_{n+1} = Q_n$ (Hold).
• When $T = 1$: $Q_{n+1} = \bar{Q}_n$ (Toggle). Divides the input clock frequency by exactly 2 ($f_{\text{out}} = f_{\text{clk}} / 2$), forming the foundational block for binary ripple counters.

1. Classification of Multivibrator Circuits

Multivibrators are regenerative switching circuits categorized by their number of permanently stable states:

1. Bistable: Two permanently stable states (Flip-Flops, Latches). Requires an external trigger pulse to transition between states.
2. Monostable (One-Shot): One stable state and one quasi-stable state. An incoming trigger pulse initiates a transition to the quasi-stable state, where it remains for a predetermined duration $\tau = R C \ln(2) \approx 0.693 R C$ before returning automatically to the stable state. Used for pulse widening, debouncing switches, and fixed-delay generation.
3. Astable (Free-Running Oscillator): Zero stable states. The circuit oscillates continuously between two quasi-stable states without external excitation, generating square wave clock signals.

2. The Schmitt Trigger & Hysteresis

Otto Schmitt (1937) invented the Schmitt Trigger, a comparator circuit with positive feedback that exhibits hysteresis—two distinct switching threshold voltages:

• Upper Trigger Point ($V_{UTP}$): When input voltage rises, output remains HIGH until $V_{\text{in}} \ge V_{UTP}$, at which point it snaps sharply to LOW.
• Lower Trigger Point ($V_{LTP}$): When input voltage falls, output remains LOW until $V_{\text{in}} \le V_{LTP}$, at which point it snaps sharply back to HIGH.
• Hysteresis Band ($\Delta V_H = V_{UTP} - V_{LTP}$): Completely rejects electrical noise and slow input voltage transitions, preventing erratic multi-trigger ringing on clock inputs.

1. Internal Architecture of the 555 Timer IC

The iconic 555 timer (Signetics, 1971) contains 23 transistors, 2 diodes, and 16 resistors integrated on silicon, structured into four functional blocks:

1. Precision Resistor Divider: Three matched $5\text{ k}\Omega$ resistors establish internal reference voltages of $\frac{2}{3} V_{CC}$ and $\frac{1}{3} V_{CC}$ (hence the name "555").
2. Threshold Comparator (Comp 1): Compares Pin 6 (Threshold) to $\frac{2}{3} V_{CC}$. If $V_{\text{thresh}} > \frac{2}{3} V_{CC}$, sets the internal flip-flop ($R=1$).
3. Trigger Comparator (Comp 2): Compares Pin 2 (Trigger) to $\frac{1}{3} V_{CC}$. If $V_{\text{trig}} < \frac{1}{3} V_{CC}$, resets the internal flip-flop ($S=1$).
4. RS Flip-Flop & Discharge Transistor ($Q_{\text{dis}}$): Drives output Pin 3 through a high-current totem-pole driver ($\pm 200\text{ mA}$) and controls Pin 7 (Discharge open-collector transistor to ground).

2. Astable Multivibrator Frequency & Duty Cycle Equations

Connected with external timing resistors $R_A, R_B$ and capacitor $C$, the capacitor charges through $R_A + R_B$ toward $V_{CC}$ and discharges through $R_B$ toward ground:

• Charge Interval ($t_{\text{high}}$): $V_C(t)$ rises from $\frac{1}{3} V_{CC}$ to $\frac{2}{3} V_{CC}$:
  $$t_{\text{high}} = (R_A + R_B) C \ln(2) \approx 0.693 (R_A + R_B) C$$
• Discharge Interval ($t_{\text{low}}$): $V_C(t)$ falls from $\frac{2}{3} V_{CC}$ to $\frac{1}{3} V_{CC}$:
  $$t_{\text{low}} = R_B C \ln(2) \approx 0.693 R_B C$$
• Total Oscillation Period ($T$):
  $$T = t_{\text{high}} + t_{\text{low}} = 0.693 (R_A + 2 R_B) C$$
• Output Frequency ($f$):
  $$f = \frac{1}{T} = \frac{1.44}{(R_A + 2 R_B) C}$$
• Duty Cycle ($D$):
  $$D = \frac{t_{\text{high}}}{T} = \frac{R_A + R_B}{R_A + 2 R_B} \times 100\%$$
  Because $R_A > 0$, standard astable connections have $D > 50\%$. Connecting a steering diode across $R_B$ bypasses $R_B$ during charging, enabling $50\%$ or lower duty cycles ($t_{\text{high}} \approx 0.693 R_A C$).