Data Conversion Systems: Digital-to-Analog & Analog-to-Digital

1. Digital-to-Analog Converter (DAC) Operational Concept

A Digital-to-Analog Converter (DAC) translates an $N$-bit digital binary word $D = b_{N-1} b_{N-2} \dots b_0$ into an equivalent proportional analog output voltage $V_{\text{out}}$ or current $I_{\text{out}}$:

where $V_{\text{ref}}$ is a precision voltage reference, and $\frac{V_{\text{ref}}}{2^N}$ defines the analog step size or resolution (1 LSB).

2. The Binary-Weighted Resistor DAC

Constructed by connecting weighted resistors $R, 2R, 4R, \dots, 2^{N-1}R$ to the inverting summing junction of an operational amplifier. Binary switches connect resistor $i$ to $-V_{\text{ref}}$ when bit $b_i = 1$, or to ground when $b_i = 0$:

Because the inverting op-amp terminal is held at virtual ground ($0\text{ V}$), the output voltage is:

3. Physical Limitations of Binary-Weighted Networks

While conceptually elegant, binary-weighted DACs are severely impractical for high resolutions ($N \ge 8$):

• Extreme Resistance Spread: For a 16-bit DAC with $R = 10\text{ k}\Omega$, the LSB resistor must be $2^{15} R = 327.68\text{ M}\Omega$—a ratio exceeding $32,000 : 1$.
• Impossibility of Monolithic Integration: Fabricating resistors spanning four orders of magnitude on a single silicon die with sub-$0.01\%$ thermal tracking is technologically impossible.

1. The R-2R Ladder Architecture

Bernard Lippel (1953) resolved the resistance spread bottleneck with the ingenious $R$-$2R$ ladder network, which utilizes only two precision resistance values—$R$ and $2R$—regardless of the bit resolution $N$.

2. Thevenin Equivalent & Constant Input Impedance Proof

Looking into any node of an $R$-$2R$ ladder toward the terminated end, the equivalent resistance is identically $R$:

1. At the termination end, two parallel $2R$ resistors combine to yield $2R \parallel 2R = R$.
2. Adding the series resistor $R$ gives $R + R = 2R$.
3. At the next node, this $2R$ is in parallel with that stage's vertical $2R$ branch: $2R \parallel 2R = R$.

By mathematical induction, this perfect binary current division repeats identically across all $N$ stages. At each ladder node, the injected current splits into two equal halves ($50\% / 50\%$).

3. Inverted R-2R Current-Steering DAC

In modern monolithic CMOS DACs, the ladder is operated in the current-steering mode: the vertical $2R$ branches terminate in SPDT CMOS switches that steer currents either into the op-amp virtual ground ($I_{\text{out}}$) or into circuit analog ground ($I_{\text{out2}}$):

Key Engineering Advantages:

• Only two resistor values ($R$ and $2R$, typically $10\text{ k}\Omega$ and $20\text{ k}\Omega$), manufactured by laser-trimmed thin-film SiCr or polysilicon with perfect thermal tracking ($< 1\text{ ppm/}^\circ\text{C}$).
• All nodes remain at fixed potentials ($0\text{ V}$), eliminating parasitic capacitance charging delays and achieving sub-nanosecond settling times.

1. DAC Resolution & Full-Scale Range (FSR)

The resolution of an $N$-bit DAC is the smallest output voltage increment it can resolve, equal to the weight of 1 LSB:

The maximum analog output, attained when all bits are 1 ($11\dots1_2$), is strictly 1 LSB below full reference:

2. Dynamic Metrics: Settling Time & Glitch Impulse

• Settling Time ($t_s$): The elapsed time from the application of an input digital transition until the analog output settles and remains within a specified error band (typically $\pm \frac{1}{2}\text{ LSB}$) of its final value. Governed by op-amp slew rate and $RC$ time constants.
• Major Carry Glitch Impulse: When transitioning across mid-scale ($0111\dots1 \to 1000\dots0$), switch timing skews cause temporary false intermediate states ($1111\dots1$ or $0000\dots0$), ejecting massive voltage spikes (glitch area in $\text{pV}\cdot\text{s}$) into audio/video signals.

3. Static Accuracy: Non-Linearity Metrics (INL & DNL)

• Differential Non-Linearity (DNL): The difference between the actual step height between adjacent codes and the ideal step height ($1\text{ LSB}$):
  $$\text{DNL}(k) = \frac{V_{\text{out}}(k) - V_{\text{out}}(k-1) - V_{\text{LSB}}}{V_{\text{LSB}}}$$
  If $\text{DNL} < -1\text{ LSB}$, the transfer function reverses direction, creating a non-monotonic DAC.
• Integral Non-Linearity (INL): The maximum deviation of the actual analog transfer curve from the ideal straight line across the entire range.

1. Operational Architecture of the Flash ADC

An Analog-to-Digital Converter (ADC) quantizes a continuous analog input voltage $V_{\text{in}}$ into a discrete digital code. The Flash (Parallel) ADC is the fastest known data conversion architecture, completing conversion in a single clock cycle ($t_{\text{conv}} < 1\text{ ns}$, gigasample/second speeds).

2. Circuit Topology

An $N$-bit Flash ADC consists of:

1. Precision Resistor Ladder: A string of $2^N$ matched resistors $R$ connected between $V_{\text{ref}}$ and ground, establishing $2^N - 1$ equally spaced reference voltage taps:
   $$V_k = \frac{k - 0.5}{2^N} V_{\text{ref}} \quad (k = 1, 2, \dots, 2^N - 1)$$
2. Comparator Bank: Exactly $2^N - 1$ analog comparators operating in parallel. Each comparator compares $V_{\text{in}}$ to its respective reference tap $V_k$. All comparators below $V_{\text{in}}$ output 1; all above output 0, producing a Thermometer Code of height proportional to $V_{\text{in}}$.
3. Priority Decoder: Converts the $(2^N - 1)$-bit thermometer code into an $N$-bit binary output word in a single gate delay.

3. Flash ADC Trade-Offs & Scaling Wall

The monumental speed of Flash ADCs is offset by exponential hardware growth:

• For $N = 2$ bits: $2^2 - 1 = 3$ comparators.
• For $N = 3$ bits: $2^3 - 1 = 7$ comparators.
• For $N = 8$ bits: $2^8 - 1 = 255$ comparators (practical limit for standalone flash).
• For $N = 16$ bits: $2^{16} - 1 = 65,535$ precision comparators on a single chip—consuming excessive silicon area and hundreds of watts of power. High resolutions require alternative multi-step architectures.

1. Successive Approximation Register (SAR) ADCs

The SAR ADC is the industry workhorse for medium-to-high resolution ($10 - 18\text{ bits}$) at sample rates up to several megasamples per second. It utilizes a feedback loop containing a DAC, a single comparator, and a digital SAR control engine executing a binary search algorithm:

1. Clock Cycle 1: SAR sets MSB to 1 ($1000\dots_2$), prompting internal DAC to output mid-scale $V_{\text{DAC}} = V_{\text{ref}} / 2$.
2. Comparator tests if $V_{\text{in}} > V_{\text{DAC}}$. If yes, MSB is retained as 1; if no, MSB is cleared to 0.
3. Clock Cycle 2: SAR sets next bit ($b_{N-2}$) to 1, tests against $V_{\text{in}}$, and retains or clears it.
4. The process repeats bit-by-bit until the LSB is resolved.

An $N$-bit SAR ADC requires exactly $N$ clock cycles per conversion ($t_{\text{conv}} = N \cdot T_{\text{clk}}$), requiring only one comparator regardless of resolution.

2. Dual-Slope Integrating ADC

The premier architecture for high-precision digital multimeters (DMMs) where ultra-high accuracy and noise immunity outweigh conversion speed ($10 - 100\text{ conversions/sec}$):

1. Run-Up Phase ($T_1$, Fixed Time): An analog integrator integrates input voltage $V_{\text{in}}$ for a fixed time interval $T_1 = 2^N T_{\text{clk}}$:
   $$V_{\text{peak}} = - \frac{1}{R C} \int_0^{T_1} V_{\text{in}} dt = - \frac{V_{\text{in}} T_1}{R C}$$
2. Run-Down Phase ($T_2$, Measured Time): Integrator switches to precision negative reference $-V_{\text{ref}}$ and discharges back to zero at a constant slope:
   $$0 = V_{\text{peak}} + \frac{V_{\text{ref}} T_2}{R C} \implies \frac{V_{\text{in}} T_1}{R C} = \frac{V_{\text{ref}} T_2}{R C}$$
   $$T_2 = T_1 \left( \frac{V_{\text{in}}}{V_{\text{ref}}} \right)$$

Monumental Advantage: Both $R$ and $C$ cancel out completely from the equation! Variations in resistor values, capacitor aging, and clock oscillator drift have zero effect on measurement accuracy. Setting $T_1 = 20\text{ ms}$ ($1/50\text{ Hz}$) provides infinite rejection of AC power line hum.