Integrated Circuit (IC) Technology & Silicon VLSI Microfabrication

1. Classification of Integrated Circuits

An Integrated Circuit (IC) is a complete electronic circuit fabricated as a single monolithic block on a thin planar substrate of single-crystal silicon. Integration density has expanded exponentially across decades (Moore's Law):

• Small-Scale Integration (SSI, 1960s): $< 12$ equivalent logic gates (e.g., 7400 quad NAND gate).
• Medium-Scale Integration (MSI, late 1960s): $12 - 100$ gates (e.g., counters, decoders, 4-bit adders).
• Large-Scale Integration (LSI, 1970s): $100 - 10,000$ gates (e.g., 8-bit microprocessors like Intel 8080, early RAMs).
• Very Large-Scale Integration (VLSI, 1980s): $10,000 - 1,000,000$ gates.
• Ultra Large-Scale Integration (ULSI / Modern Nanoscale): $> 10^{9} - 10^{11}$ transistors on a single $200\text{ mm}^2$ chip (e.g., multi-core CPUs, GPUs with 80+ billion transistors).

2. Electronic Grade Silicon (EGS) & The Czochralski (CZ) Method

Microfabrication begins with raw quartzite sand ($\text{SiO}_2$), reduced in an electric arc furnace to Metallurgical Grade Silicon (MGS, $\sim 98\%$ pure). Chemical chlorination produces gaseous trichlorosilane ($\text{SiHCl}_3$), which is fractionally distilled and reduced with hydrogen to synthesize polycrystalline Electronic Grade Silicon (EGS) with impurity levels below 1 part per billion ($< 10^{-9}$).

To convert poly-silicon into a dislocation-free single crystal, Jan Czochralski's (1918) crystal pulling method is employed:

1. EGS is melted in a high-purity fused silica crucible at $1420^\circ\text{C}$ in an inert Argon atmosphere. Controlled $p$-type (Boron) or $n$-type (Phosphorus) dopants are added.
2. A small single-crystal seed of precise crystallographic orientation ($\langle 100 \rangle$ or $\langle 111 \rangle$) is lowered into the melt surface.
3. The seed crystal is slowly rotated and pulled upward ($1 - 2\text{ mm/min}$). Surface tension and heat extraction cause silicon atoms in the melt to freeze onto the seed in identical crystalline lattice orientation, producing a massive cylindrical single-crystal ingot (boule) up to $300\text{ mm}$ ($12\text{ inches}$) in diameter and weighing over $100\text{ kg}$.

3. Wafer Shaping and Chemical-Mechanical Planarization (CMP)

The ingot is ground to uniform diameter, flat or notched for crystal orientation alignment, and sliced into thin discs ($775\text{ \mu m}$ thick) using diamond-coated high-speed wire saws. Wafers undergo edge rounding, chemical etching to relieve surface mechanical damage, and multi-stage Chemical-Mechanical Planarization (CMP) using colloidal silica slurry to achieve an atomically flat, mirror-polished surface with root-mean-square roughness $< 0.1\text{ nm}$.

1. Epitaxial Layer Growth

Epitaxy (from Greek epi "upon" and taxis "ordered") is the deposition of a thin single-crystal silicon layer ($0.5 - 5\text{ \mu m}$) onto the substrate wafer, continuing the substrate's exact crystalline lattice. Unlike bulk substrates, the epitaxial layer's dopant type and concentration can be tailored with atomic precision. In Vapor-Phase Epitaxy (VPE), silicon tetrachloride gas is reduced at $1200^\circ\text{C}$:

2. Silicon Dioxide ($\text{SiO}_2$) Thermal Oxidation

Silicon's pre-eminence as the king of semiconductor materials stems from its native oxide: silicon dioxide ($\text{SiO}_2$), a chemically robust, impermeable dielectric insulator with an enormous band gap ($9.0\text{ eV}$), high breakdown electric field ($10^7\text{ V/cm}$), and exceptional dielectric masking properties against chemical dopants.

Wafers are heated in high-temperature quartz tube furnaces ($900 - 1100^\circ\text{C}$):

• Dry Oxidation: $\text{Si} + \text{O}_2 \to \text{SiO}_2$. Slower growth rate, but yields ultra-dense oxide with low interface trap density ($\sim 10^{10}\text{ cm}^{-2}$). Used for thin MOSFET gate oxides.
• Wet Oxidation (Steam): $\text{Si} + 2\text{H}_2\text{O} \to \text{SiO}_2 + 2\text{H}_2$. Grows oxide 5 to 10 times faster due to high solubility of $\text{H}_2\text{O}$ in silica. Used for thick field isolation oxides ($300 - 500\text{ nm}$).

3. The Deal-Grove Oxidation Kinetics Model

Bruce Deal and Andrew Grove (1965) formulated the kinetics of thermal oxidation. As oxide grows to thickness $x_0$, oxidant species must diffuse through the existing oxide layer before reacting at the $\text{Si}\text{-}\text{SiO}_2$ interface:

where $B$ is the parabolic rate constant ($\mu\text{m}^2/\text{hr}$), $B/A$ is the linear rate constant ($\mu\text{m/hr}$), and $\tau$ accounts for any initial oxide layer. Solving the quadratic equation:

• Linear Regime ($t \ll A^2 / 4B$, Thin Oxides): Growth is limited by chemical reaction rate at the silicon interface:
  $$x_0(t) \approx \frac{B}{A}(t + \tau)$$
• Parabolic Regime ($t \gg A^2 / 4B$, Thick Oxides): Growth is limited by diffusion of oxidant molecules through the thick oxide layer:
  $$x_0^2(t) \approx B \cdot t \implies x_0(t) \propto \sqrt{t}$$

1. The Photolithographic Process Sequence

Photolithography is the optical printing process that transfers microscopic geometric circuit patterns from a photographic mask (reticle) onto the wafer surface:

1. Surface Preparation & HMDS Priming: Hexamethyldisilazane (HMDS) vapor prime makes the hydrophilic $\text{SiO}_2$ surface hydrophobic to ensure photoresist adhesion.
2. Spin Coating: A liquid light-sensitive polymeric photoresist is dispensed onto the wafer, spun at $3000 - 5000\text{ RPM}$ to form a uniform thin film ($0.5 - 1.0\text{ \mu m}$).
3. Soft Bake: Heated to $90 - 100^\circ\text{C}$ to evaporate solvents.
4. Mask Alignment & Exposure: High-precision reduction stepper lenses project UV light through a photomask.
   • Positive Photoresist (Diazoquinone/Novolac): Exposed regions undergo photochemical scission, becoming highly soluble in alkaline aqueous developer solution. Unexposed regions remain insoluble. Leaves an exact duplicate of the dark mask pattern. Standard in VLSI due to superior resolution.
   • Negative Photoresist (Polyisoprene): Exposed regions cross-link and polymerize, becoming insoluble. Leaves the photographic negative. Swells during development, limiting resolution.
5. Post-Exposure Bake & Development: Dissolves soluble resist regions, exposing the underlying $\text{SiO}_2$ film.
6. Hard Bake ($120 - 140^\circ\text{C}$): Hardens the resist polymer for etch resistance.
7. Etching: Pattern transfer into the underlying material.
   • Wet Chemical Etching: Buffered Oxide Etch (BOE / HF). Isotropic (etches equally in all directions), producing undesirable lateral undercut.
   • Dry Plasma / Reactive-Ion Etching (RIE): High-energy reactive ions in an anisotropic RF plasma etch vertically with near-zero lateral undercut, preserving sub-micron feature fidelity.
8. Photoresist Stripping: Removed via oxygen plasma ashing ($\text{O}_2$ plasma incinerates organic resist to $\text{CO}_2$ and $\text{H}_2\text{O}$).

2. Optical Resolution Limits & EUV Lithography

The minimum resolvable feature size ($CD$, Critical Dimension) is governed by the Rayleigh diffraction criterion:

where $\lambda$ is illumination wavelength, $NA = n\sin\theta$ is numerical aperture, and $k_1$ is a process factor ($\ge 0.25$). Modern semiconductor fabrication transitioned from Mercury arc lamps (G-line $436\text{ nm}$, I-line $365\text{ nm}$) to Excimer lasers (KrF $248\text{ nm}$, ArF $193\text{ nm}$ immersion lithography with water $n=1.44$). For sub-$7\text{ nm}$ nodes, state-of-the-art foundries utilize Extreme Ultraviolet (EUV) lithography ($\lambda = 13.5\text{ nm}$) generated by pulsing high-power $\text{CO}_2$ lasers into molten tin droplets in ultra-high vacuum.

1. Thermal Furnace Diffusion

Impurity doping introduces group-III acceptors (Boron) or group-V donors (Phosphorus, Arsenic) into the silicon crystal lattice. In classical thermal diffusion, wafers in a quartz furnace ($900 - 1200^\circ\text{C}$) are exposed to a gaseous dopant source ($\text{POCl}_3, \text{BBr}_3$):

1. Predeposition (Constant Source Diffusion): Dopant surface concentration is held fixed at solid solubility limit $C_s$. Governed by Fick's Second Law:
   $$\frac{\partial C(x,t)}{\partial t} = D \frac{\partial^2 C(x,t)}{\partial x^2}$$
   Boundary conditions ($C(0,t) = C_s, C(\infty,t) = 0$) yield the Complementary Error Function (erfc) profile:
   $$C(x, t) = C_s \operatorname{erfc}\left( \frac{x}{2 \sqrt{Dt}} \right)$$
2. Drive-In Diffusion (Limited Source): Dopant vapor is shut off; the fixed deposited dose $Q$ drives deeper into the silicon at higher temperature, forming a Gaussian profile:
   $$C(x, t) = \frac{Q}{\sqrt{\pi D t}} \exp\left( - \frac{x^2}{4 D t} \right)$$

Thermal diffusion is isotropic: dopants diffuse laterally under mask edges by $70 - 80\%$ of the vertical junction depth ($x_{\text{lat}} \approx 0.8 x_j$), making it obsolete for shallow sub-micron source/drain junctions.

2. High-Energy Ion Implantation

The dominant doping technique in modern VLSI. Dopant atoms are ionized in an arc source, accelerated through high electrostatic potential differences ($10\text{ keV} - 3\text{ MeV}$), mass-analyzed using a bending dipole electromagnet to guarantee $100\%$ chemical purity, and fired directly into the silicon wafer.

According to Lindhard-Scharff-Schiøtt (LSS) stopping theory, the dopant profile follows a Gaussian distribution centered at the Projected Range ($R_p$) with standard deviation Projected Straggle ($\Delta R_p$):

where $\Phi$ is the implanted ion dose (ions/$\text{cm}^2$). The peak concentration occurs at depth $x = R_p$:

Advantages over diffusion: Independent control of depth (via acceleration energy) and dose (via beam current integration); near-zero lateral straggle; room temperature operation; compatibility with photoresist masks.

Post-Implant Thermal Annealing: High-energy ion bombardment shatters the crystalline silicon lattice into an amorphous layer. Rapid Thermal Annealing (RTA, $1000^\circ\text{C}$ for seconds) recrystallizes the damaged lattice and shifts dopant atoms into substitutional lattice sites where they become electrically active.

1. Complete Monolithic CMOS Fabrication Sequence (Self-Aligned Twin-Well)

Fabricating a complementary pair of nMOS and pMOS transistors on a single substrate requires a sequence of approximately 30 lithographic mask levels:

1. Starting Substrate: Lightly doped $p$-type $\langle 100 \rangle$ silicon wafer.
2. Well Formation: Ion implantation of Phosphorus followed by high-temperature drive-in forms the $n$-well (in which pMOS transistors will reside).
3. Shallow Trench Isolation (STI): Etch narrow vertical trenches ($300\text{ nm}$ deep) between active transistor areas, fill with CVD $\text{SiO}_2$, and planarize via CMP to eliminate parasitic latchup.
4. Gate Stack: Thermally grow ultra-thin gate dielectric ($\text{SiO}_2$ or high-$\kappa$ Hafnium dioxide $\text{HfO}_2$), deposit polycrystalline silicon (polysilicon) or metal gate layer, pattern via lithography, and etch vertical gate electrodes.
5. Lightly Doped Drain (LDD) Implantation: Shallow low-dose implants under gate edges suppress hot-carrier degradation.
6. Dielectric Sidewall Spacers: Conformally deposit $\text{Si}_3\text{N}_4$ or $\text{SiO}_2$ and anisotropically plasma etch to leave insulating spacer sidewalls along gate edges.
7. Source/Drain Self-Aligned Implantation:
   • $n^+$ Implantation (Arsenic/Phosphorus) forms nMOS source/drain regions. The polysilicon gate acts as an impenetrable mask, naturally aligning the channel edges (Self-Aligned Gate).
   • $p^+$ Implantation (Boron) forms pMOS source/drain regions.
8. Salicidation (Self-Aligned Silicide): Deposit thin Cobalt or Nickel, anneal at $700^\circ\text{C}$ to form low-resistance metal silicide ($\text{NiSi}$) on all exposed silicon contacts and polysilicon gates, reducing contact resistance.
9. Pre-Metal Dielectric (PMD) & Tungsten Contacts: Deposit thick planarizing oxide, plasma etch contact vias down to source/drain/gate regions, and fill with refractory Tungsten (W) plugs.
10. Multi-Level Metallization: Deposit alternating copper (Cu) interconnect wire layers separated by low-$\kappa$ dielectric insulators using the dual-damascene electroplating process (up to 12 - 15 metal wiring levels).
11. Passivation & Wire Bonding: Deposit protective silicon nitride ($\text{Si}_3\text{N}_4$) scratch coat, etch bond pad openings, slice die, mount to ceramic/plastic leadframe, bond gold/copper wires, and encapsulate in epoxy resin.

2. Integrated Passive Components & Sheet Resistance ($R_s$)

Passive circuit components inside integrated circuits:

• Diffused Resistors: A semiconductor layer of length $L$, width $W$, thickness $t$, and resistivity $\rho$ has resistance:
  $$R = \rho \frac{L}{A} = \frac{\rho}{t} \left(\frac{L}{W}\right) = R_s \left(\frac{L}{W}\right)$$
  where $R_s = \rho / t$ is the Sheet Resistance, expressed in units of Ohms per square ($\Omega/\square$). The ratio $L/W$ represents the number of squares. Right-angle square corners contribute approximately $0.56$ squares each due to current crowding.
• MOS Capacitors: Formed by gate polysilicon electrode over thin dielectric oxide over an $n^+$ diffused silicon bottom plate:
  $$C = \frac{\varepsilon_{\text{ox}} \varepsilon_0 A}{t_{\text{ox}}}$$