Transistors: BJT, JFET & MOSFET Biasing Circuits

1. Physical Structure of the Bipolar Junction Transistor

A bipolar junction transistor (BJT) consists of a single crystal of semiconductor with three alternating doped regions forming two back-to-back PN junctions:

• Emitter ($E$): Heavily doped ($N_E \gg 10^{19}\text{ cm}^{-3}$) to inject a massive stream of majority carriers into the base. Moderate geometric physical width.
• Base ($B$): Extremely narrow ($W_B \ll L_n, L_p$, typically $< 1\;\mu\text{m}$) and lightly doped ($N_B \sim 10^{16}\text{ cm}^{-3}$) to minimize electron-hole recombination so that nearly all injected carriers traverse it safely.
• Collector ($C$): Moderately doped and physically largest in volume to dissipate heat generated by carrier collection under high reverse bias voltages.

Transistors are fabricated in two complementary polarity types: NPN (majority carriers electrons) and PNP (majority carriers holes).

2. The Transistor Action Mechanism (NPN in Active Mode)

To operate a BJT as a linear amplifier in the forward-active mode:

1. The Base-Emitter (B-E) junction is forward-biased ($V_{BE} \approx 0.7\text{ V}$ for Silicon).
2. The Collector-Base (C-B) junction is reverse-biased ($V_{CB} > 0$, typically $5\text{ V} - 20\text{ V}$).

Because the B-E junction is forward-biased, the heavily doped emitter injects a large flux of electrons into the base. Because the base is extremely thin ($W_B \ll L_n$) and lightly doped, only a tiny fraction (typically $< 1\%$) of electrons recombine with base holes, contributing to the tiny base current $I_B$. The remaining $> 99\%$ of electrons diffuse across the base to the edge of the reverse-biased collector-base space-charge layer, where the strong electric field sweeps them across into the collector, constituting the collector current $I_C$.

3. Terminal Current Relations

By Kirchhoff's Current Law: The fraction of emitter current collected is the common-base current gain $\alpha$: Typically, $\alpha$ ranges between $0.98$ and $0.998$. Here $I_{CBO}$ is the tiny collector-to-base reverse leakage current with emitter open.

1. Common Base (CB) Configuration

The base terminal is common to both input (emitter-base) and output (collector-base) circuits.

• Input Characteristics: Curve of $I_E$ vs. $V_{EB}$ at constant $V_{CB}$. Resembles a forward-biased diode. Dynamic input resistance is very low ($R_{\text{in}} \approx 20\,\Omega - 50\,\Omega$).
• Output Characteristics: Curve of $I_C$ vs. $V_{CB}$ at constant $I_E$. In the active region, $I_C$ is nearly horizontal and independent of $V_{CB}$, yielding high output resistance ($R_{\text{out}} \approx 1\text{ M}\Omega$).
• Current Gain: $\alpha = \Delta I_C / \Delta I_E < 1$ (no current amplification; provides voltage and power gain).

2. Common Emitter (CE) Configuration (Most Widely Used)

The emitter terminal is grounded/common to both input (base-emitter) and output (collector-emitter) circuits.

• Current Gain $\beta$ (or $h_{fe}$):
  $$I_C = \alpha I_E + I_{CBO} = \alpha (I_B + I_C) + I_{CBO} \implies I_C(1 - \alpha) = \alpha I_B + I_{CBO}$$
  $$I_C = \left( \frac{\alpha}{1 - \alpha} \right) I_B + \left( \frac{1}{1 - \alpha} \right) I_{CBO} = \beta I_B + I_{CEO}$$
  where the common-emitter current gain $\beta$ is:
  $$\beta = \frac{\alpha}{1 - \alpha}, \quad \alpha = \frac{\beta}{1 + \beta}$$
  Typically, $\beta$ ranges from $50$ to $300$. The collector-to-emitter leakage current is $I_{CEO} = (1 + \beta) I_{CBO}$.
• Input Characteristics: $I_B$ vs. $V_{BE}$ for constant $V_{CE}$. Input resistance $R_{\text{in}} \approx 1\text{ k}\Omega - 2\text{ k}\Omega$.
• Output Characteristics: $I_C$ vs. $V_{CE}$ for constant $I_B$. Shows three operating regions:
  1. Active Region: B-E forward-biased, C-B reverse-biased ($V_{CE} > 0.3\text{ V}$). Curves have a slight upward slope due to base-width modulation (Early effect). Ideal for linear amplification.
  2. Saturation Region: Both B-E and C-B forward-biased ($V_{CE} < V_{CE(\text{sat})} \approx 0.2\text{ V}$). Transistor acts as an ON switch with negligible voltage drop.
  3. Cutoff Region: Both B-E and C-B reverse-biased ($I_B = 0, I_C = I_{CEO} \approx 0$). Transistor acts as an OFF switch.

3. Common Collector (CC) Configuration (Emitter Follower)

Collector is AC ground. Input applied to base, output extracted from emitter. Features very high input impedance ($R_{\text{in}} > 100\text{ k}\Omega$), very low output impedance ($R_{\text{out}} < 50\,\Omega$), and near-unity voltage gain ($A_v \approx 1$). Used ubiquitously for impedance matching and output buffer stages.

1. The DC Load Line

Consider a Common Emitter circuit with collector supply voltage $V_{CC}$ and collector load resistor $R_C$. Applying Kirchhoff's Voltage Law to the output loop: This is the equation of a straight line on the $I_C - V_{CE}$ output characteristic plane, termed the DC Load Line:

• Cutoff Point (X-axis intercept): Set $I_C = 0 \implies V_{CE} = V_{CC}$.
• Saturation Point (Y-axis intercept): Set $V_{CE} = 0 \implies I_C = \frac{V_{CC}}{R_C}$.
• Slope: $-\frac{1}{R_C}$.

2. The Quiescent Operating Point (Q-Point)

The intersection of the DC load line with the transistor output characteristic corresponding to the base bias current $I_B$ establishes the quiescent operating point (Q-point) $(V_{CEQ}, I_{CQ})$. For maximum symmetrical undistorted output voltage swing (Class A operation), the Q-point should be positioned precisely at the midpoint of the DC load line:

3. The AC Load Line

When an external load $R_L$ is capacitively coupled to the collector, the effective AC load resistance seen by the collector signal is $r_c = R_C \parallel R_L$. Because $r_c < R_C$, the AC load line passes through the same DC Q-point $(V_{CEQ}, I_{CQ})$ but has a steeper slope $-\frac{1}{r_c}$: The maximum peak-to-peak undistorted output voltage swing is limited by the distance to cutoff or saturation along the AC load line:

1. Need for Biasing & Thermal Runaway

The Q-point coordinates $(I_C, V_{CE})$ are temperature-sensitive due to three factors:

1. Reverse saturation current $I_{CBO}$ doubles approximately every $10^\circ\text{C}$ rise in temperature.
2. Base-emitter voltage $V_{BE}$ decreases at a rate of approximately $-2.5\text{ mV}/^\circ\text{C}$.
3. Current gain $\beta$ increases with temperature.

Without proper stabilization, an increase in temperature causes $I_C$ to rise, increasing collector power dissipation $P_C = V_{CE} I_C$. This heats the junction further, causing a catastrophic regenerative positive feedback loop known as thermal runaway.

2. Definition of Stability Factor $S$

The stability factor $S$ is defined as the rate of change of collector current with respect to leakage current $I_{CBO}$: An ideal bias circuit has $S \to 1$ (complete thermal immunity). Higher values ($S \gg 1$) indicate severe instability.

3. Comparative Analysis of Biasing Topologies

• Fixed Base Resistor Bias: A single resistor $R_B$ connects from $V_{CC}$ to the base:
  $$I_B = \frac{V_{CC} - V_{BE}}{R_B} \approx \text{const} \implies S = 1 + \beta$$
  For $\beta = 100$, $S = 101$. Extremely unstable; completely unsuitable for linear amplifiers.
• Collector Feedback Bias: $R_B$ is connected directly from the collector to the base:
  $$S = \frac{1 + \beta}{1 + \beta \frac{R_C}{R_C + R_B}}$$
  Provides negative feedback: if $I_C$ rises, $V_C = V_{CC} - I_C R_C$ drops, reducing $I_B$ and checking the rise. Moderate stability.
• Voltage Divider Bias (Universal Bias): Two resistors $R_1, R_2$ form a potential divider across $V_{CC}$, combined with an emitter degeneration resistor $R_E$:
  $$V_{\text{th}} = V_{CC} \frac{R_2}{R_1 + R_2}, \quad R_{\text{th}} = R_1 \parallel R_2 = \frac{R_1 R_2}{R_1 + R_2}$$
  The input loop equation is $V_{\text{th}} = I_B R_{\text{th}} + V_{BE} + I_E R_E$. Differentiating delivers the stability factor:
  $$S = \frac{1 + \beta}{1 + \beta \left( \frac{R_E}{R_{\text{th}} + R_E} \right)}$$
  By designing $R_{\text{th}} \ll \beta R_E$ (rule of thumb: $R_{\text{th}} \le 0.1 \beta R_E$ or $R_2 \le 0.1 \beta R_E$), the fraction approaches 1:
  $$S \approx \frac{1 + \beta}{1 + \beta} = 1$$
  The Q-point becomes virtually independent of transistor $\beta$ and temperature variations.

1. Junction Field Effect Transistor (JFET)

The JFET is a unipolar three-terminal device where conduction is governed entirely by majority carriers through a semiconductor channel controlled by an electric field:

• Construction: An N-channel JFET consists of a lightly doped n-type silicon bar with Ohmic contacts at both ends designated Drain ($D$) and Source ($S$). Two heavily doped $p^+$ regions diffused on opposite sides are connected to form the Gate ($G$).
• Pinch-Off Voltage $V_P$: Operating with reverse-biased gate-source junction ($V_{GS} \le 0$). Reverse bias widens the depletion regions into the channel. At a critical drain-source voltage $V_{DS} = V_{DS(\text{sat})} = V_{GS} - V_P$, the two depletion boundaries touch at the drain end, a condition termed pinch-off. Beyond pinch-off, the drain current saturates at an almost constant level.
• Shockley's Drain Current Equation: In the saturation/active region ($V_{DS} \ge V_{GS} - V_P$):
  $$I_D = I_{DSS} \left( 1 - \frac{V_{GS}}{V_P} \right)^2$$
  where $I_{DSS}$ is the maximum saturation drain current at $V_{GS} = 0$.
• Transconductance $g_m$:
  $$g_m = \frac{\partial I_D}{\partial V_{GS}} = \frac{2 I_{DSS}}{|V_P|} \left( 1 - \frac{V_{GS}}{V_P} \right) = g_{m0} \left( 1 - \frac{V_{GS}}{V_P} \right)$$

2. Metal-Oxide-Semiconductor FETs (MOSFETs)

The gate electrode is physically insulated from the channel by an ultra-thin dielectric layer of Silicon Dioxide ($\text{SiO}_2$), resulting in an astronomical input impedance ($R_{\text{in}} > 10^{12}\,\Omega$):

• Depletion-Type MOSFET (D-MOSFET): Fabricated with a physical channel. Can operate in either depletion mode (negative $V_{GS}$ repels channel electrons) or enhancement mode (positive $V_{GS}$ attracts additional electrons, boosting $I_D$ above $I_{DSS}$). Follows Shockley's square-law equation for both positive and negative $V_{GS}$.
• Enhancement-Type MOSFET (E-MOSFET): The cornerstone of modern VLSI and microprocessor technology (CMOS). Has no physical channel at zero bias ($I_D = 0$ at $V_{GS} = 0$). When $V_{GS}$ exceeds the positive threshold voltage $V_{th}$, an inversion layer forms at the $\text{Si}-\text{SiO}_2$ interface, creating an n-channel. In saturation ($V_{DS} \ge V_{GS} - V_{th}$):
  $$I_D = k_n (V_{GS} - V_{th})^2 = \frac{1}{2} \mu_n C_{ox} \left( \frac{W}{L} \right) (V_{GS} - V_{th})^2$$
  where $C_{ox} = \varepsilon_{ox}/t_{ox}$ is the gate oxide capacitance per unit area, and $W/L$ is the transistor aspect ratio.