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Chapter 7 • Theory & Derivations

Operational Amplifiers (Op-Amps) & Linear Analog Computing

Comprehensive mathematical exposition of operational amplifiers: ideal characteristics vs. practical silicon limits; the Virtual Ground theorem; inverting, non-inverting, and buffer topologies; summing adders, difference subtractors, and high-CMRR 3-op-amp instrumentation amplifiers; exact derivations and stability criteria for practical analog integrators and differentiators.

§7.1 Ideal Op-Amp Model, 741 Architecture & Virtual Ground Concept

1. Ideal Op-Amp Characteristics vs. Practical 741 IC

An Operational Amplifier (Op-Amp) is a direct-coupled, high-gain differential voltage amplifier. The ideal op-amp model provides an indispensable mathematical abstraction for circuit analysis:

Parameter Ideal Value Typical Practical IC (uA741) Physical Implication
Open-Loop Voltage Gain ($A_{OL}$) $A_{OL} \to \infty$ $2 \times 10^5$ ($106\,\text{dB}$) Differential input voltage is forced to near zero
Input Impedance ($R_{in}$) $R_{in} \to \infty$ $2\,\text{M}\Omega$ (BJT) / $10^{12}\,\Omega$ (FET) Draws zero current from driving source ($I^+ = I^- = 0$)
Output Impedance ($R_{out}$) $R_{out} = 0$ $75\,\Omega$ Can drive any load resistance without terminal voltage drop
Bandwidth ($BW$) $BW \to \infty$ $1\,\text{MHz}$ (Unity Gain $f_T$) Amplifies signals uniformly from DC to high frequencies
Input Offset Voltage ($V_{os}$) $V_{os} = 0$ $1\text{ to }5\,\text{mV}$ $V_o = 0$ when differential input is strictly zero
CMRR $\text{CMRR} \to \infty$ $90\,\text{dB}$ Completely rejects common-mode noise and interference

2. The Golden Rules & Virtual Ground Principle

In any linear op-amp circuit operating under negative feedback where output remains unclipped between the supply rails ($-V_{EE} < V_o < +V_{CC}$), two fundamental axioms (the Golden Rules) govern behavior:

  1. Axiom 1 (Virtual Short): The voltage difference between the inverting input ($-$) and non-inverting input ($+$) is infinitesimally small:
    $$V_d = V^+ - V^- = \frac{V_o}{A_{OL}} \xrightarrow{A_{OL} \to \infty} 0 \implies V^- = V^+$$
    When the non-inverting terminal is connected to physical ground ($V^+ = 0$), the inverting terminal is held at ground potential ($V^- = 0$) by the feedback loop. This node is termed a Virtual Ground: it has the potential of ground ($0\,\text{V}$), yet no current can flow directly to physical earth through the terminal.
  2. Axiom 2 (Zero Input Bias Current): Because input impedance is infinite ($R_{in} \to \infty$), no current enters either input terminal:
    $$I^+ = I^- = 0$$
    All incoming signal currents are forced entirely into the feedback loop.

§7.2 Fundamental Closed-Loop Configurations: Inverting, Non-Inverting & Buffer

1. Inverting Amplifier Configuration

In the inverting amplifier, input voltage $v_{in}$ is applied through resistor $R_1$ to the inverting terminal ($-$), with feedback resistor $R_f$ connected from output $v_o$ back to the inverting terminal. The non-inverting terminal ($+$) is tied to ground ($V^+ = 0$).

By Axiom 1, $V^- = V^+ = 0\,\text{V}$ (virtual ground). Applying Kirchhoff's Current Law at the inverting summing node:

$$I_1 = I_f + I^-$$

Since $I^- = 0$, $I_1 = I_f$:

$$\frac{v_{in} - V^-}{R_1} = \frac{V^- - v_o}{R_f} \implies \frac{v_{in} - 0}{R_1} = \frac{0 - v_o}{R_f}$$

Solving for the closed-loop voltage gain $A_v$:

$$A_v = \frac{v_o}{v_{in}} = - \frac{R_f}{R_1}$$

The input impedance seen by the source is strictly $Z_{in} = R_1$. Output impedance is $Z_{out} \approx 0$.

2. Non-Inverting Amplifier Configuration

In the non-inverting amplifier, input voltage $v_{in}$ is applied directly to the high-impedance non-inverting terminal ($+$), so $V^+ = v_{in}$. Resistors $R_1$ and $R_f$ form a voltage divider from output $v_o$ to ground, feeding the inverting node.

By Axiom 1, $V^- = V^+ = v_{in}$. Applying KCL at the inverting node:

$$\frac{0 - V^-}{R_1} + \frac{v_o - V^-}{R_f} = 0 \implies \frac{v_o - v_{in}}{R_f} = \frac{v_{in}}{R_1}$$
$$v_o = v_{in} \left( 1 + \frac{R_f}{R_1} \right)$$

Thus, the non-inverting gain is always positive and strictly $\ge 1$:

$$A_v = \frac{v_o}{v_{in}} = 1 + \frac{R_f}{R_1}$$

Input impedance is extremely high ($Z_{in} \approx R_{in} (1 + A_{OL}\beta) \sim 10^{9}\,\Omega$ for BJT), preventing any loading on preceding stages.

3. Voltage Follower (Unity-Gain Buffer)

Setting $R_f = 0$ (direct short from output to inverting terminal) and $R_1 = \infty$ (open circuit):

$$A_v = 1 + \frac{0}{\infty} = 1 \implies v_o = v_{in}$$

The voltage follower provides unity voltage gain, zero phase shift, astronomical input impedance ($Z_{in} \to \infty$), and near-zero output impedance ($Z_{out} \to 0$). It acts as the universal impedance-matching buffer, isolating sensitive high-impedance sensors (such as pH glass electrodes or piezoelectric transducers) from low-impedance measuring loads.

§7.3 Linear Operations: Summing Adder & Difference Amplifier

1. Inverting Summing Amplifier (Analog Adder)

Multiple input voltages $v_1, v_2, \dots, v_n$ are connected through respective resistors $R_1, R_2, \dots, R_n$ to the common inverting virtual ground node. Applying KCL:

$$I_1 + I_2 + \dots + I_n = I_f$$
$$\frac{v_1 - 0}{R_1} + \frac{v_2 - 0}{R_2} + \dots + \frac{v_n - 0}{R_n} = \frac{0 - v_o}{R_f}$$

Solving for output voltage $v_o$:

$$v_o = - \left( \frac{R_f}{R_1} v_1 + \frac{R_f}{R_2} v_2 + \dots + \frac{R_f}{R_n} v_n \right)$$

If all input resistors are chosen equal ($R_1 = R_2 = \dots = R_n = R$):

$$v_o = - \frac{R_f}{R} (v_1 + v_2 + \dots + v_n)$$

By selecting binary-weighted resistor values ($R, 2R, 4R, 8R$), the summing amplifier operates as a digital-to-analog converter (DAC).

2. Difference Subtractor Amplifier

The difference amplifier rejects common-mode voltages and amplifies the differential voltage between two signals $v_1$ and $v_2$. Applying superposition or voltage division:

At non-inverting terminal ($+$): $V^+ = v_2 \left( \frac{R_4}{R_3 + R_4} \right)$.

At inverting terminal ($-$), using virtual short $V^- = V^+$ and nodal analysis:

$$v_o = - \frac{R_2}{R_1} v_1 + \left( 1 + \frac{R_2}{R_1} \right) \left( \frac{R_4}{R_3 + R_4} \right) v_2$$

Setting the bridge balance condition $\frac{R_2}{R_1} = \frac{R_4}{R_3}$:

$$v_o = \frac{R_2}{R_1} (v_2 - v_1)$$

The circuit precisely subtracts $v_1$ from $v_2$ with differential gain $A_d = R_2 / R_1$. Any common-mode noise present equally on both leads cancels out.

3. Three-Op-Amp Instrumentation Amplifier

While the single op-amp difference amplifier is simple, its input impedances are low and asymmetrical ($Z_{in1} = R_1$, $Z_{in2} = R_3 + R_4$).

The Three-Op-Amp Instrumentation Amplifier overcomes this by placing two non-inverting buffers ($A_1, A_2$) before the differential stage ($A_3$). Differential gain is set by a single variable gain resistor $R_G$:

$$A_d = \left( 1 + \frac{2 R_1}{R_G} \right) \left( \frac{R_3}{R_2} \right)$$

Common-mode signals pass through the input buffers with unity gain ($A_{cm,1} = 1$) while differential signals are heavily amplified, yielding common-mode rejection ratios exceeding $120\,\text{dB}$ with gigohm input impedances.

§7.4 Analog Integrator & Differentiator: Ideal vs. Practical Frequency Response

1. Ideal Op-Amp Integrator

Replacing the feedback resistor $R_f$ with a capacitor $C$ in an inverting configuration yields an integrator. By virtual ground ($V^- = 0$):

$$i_{in}(t) = \frac{v_{in}(t)}{R}, \quad i_f(t) = C \frac{d(0 - v_o)}{dt} = - C \frac{d v_o}{dt}$$

Equating currents $i_{in} = i_f$ and integrating from $t = 0$ to $t$:

$$v_o(t) = - \frac{1}{R C} \int_{0}^{t} v_{in}(\tau)\, d\tau + v_o(0)$$

In Laplace transform domain:

$$H(s) = \frac{V_o(s)}{V_{in}(s)} = - \frac{1}{s R C}$$

The DC Drift/Saturation Problem: At DC ($s \to 0$ or $\omega = 0$), capacitor impedance is infinite ($X_C \to \infty$). The op-amp operates open-loop with astronomical DC gain $A_{OL} \sim 10^5$. Any minuscule input offset voltage $V_{os}$ or bias current $I_B$ charges the capacitor continually, driving the op-amp into saturation at $\pm V_{sat}$ within seconds!

2. Practical (Lossy) Integrator

To prevent DC saturation, a large stabilizing resistor $R_f$ (typically $10 R$ to $100 R$) is placed in parallel with $C$. The transfer function becomes:

$$H(s) = - \frac{R_f \parallel \frac{1}{sC}}{R} = - \frac{ \frac{R_f}{1 + s R_f C} }{R} = - \frac{R_f / R}{1 + s R_f C}$$

At DC ($\omega = 0$), the gain is securely clamped to a finite value $A_{dc} = - R_f / R$.

The lower corner frequency separating amplifier behavior from true integration is:

$$f_L = \frac{1}{2\pi R_f C}$$

For input frequencies $f \gg f_L$ (at least $10 f_L$), the capacitor impedance dominates $R_f$, and the circuit performs pure integration with a $-20\,\text{dB/decade}$ roll-off.

3. Ideal vs. Practical Differentiator

Inverting the positions—placing $C$ at input and $R$ in feedback—produces an ideal differentiator:

$$v_o(t) = - R C \frac{d v_{in}}{dt}$$
$$H(s) = - s R C \implies |H(j\omega)| = \omega R C$$

The Noise and Instability Problem: Gain $|H(j\omega)|$ increases linearly with frequency at $+20\,\text{dB/decade}$ indefinitely! High-frequency thermal noise, radio pickup, and power transients are amplified enormously, overwhelming the desired signal and causing parasitic oscillations.

Practical Differentiator: A small resistor $R_1$ is added in series with $C$, and a small capacitor $C_f$ is placed in parallel with $R_f$. The high-frequency cutoff is set to:

$$f_H = \frac{1}{2\pi R_1 C} = \frac{1}{2\pi R_f C_f}$$

For frequencies $f \ll f_H$, the circuit differentiates cleanly; for frequencies $f > f_H$, the response rolls off at $-20\,\text{dB/decade}$, guaranteeing total high-frequency noise immunity and closed-loop stability.

Solved Problem Example 7.1: Design of Analog Computing Linear Combination Circuit

Using standard op-amps operating with dual $\pm 15\text{ V}$ supplies and resistors in the range $10\text{ k}\Omega$ to $100\text{ k}\Omega$, design a summing amplifier circuit to produce an output voltage: $v_o = - (3 v_1 + 5 v_2 - 2 v_3)$. (a) Draw the schematic diagram using inverting amplifier stages. (b) Calculate the precise values for all resistors ($R_1, R_2, R_3, R_f$). (c) Determine the maximum allowable positive and negative excursions of input voltages before the output clips at $\pm 13.5\text{ V}$.

Step 1: Circuit Topology Architecture

Because an inverting summing amplifier produces an inverted sum $- (\sum k_i v_i)$, we can invert $v_1$ and $v_3$ first using inverting unity/gain stages, or invert the output of a summing amplifier:

Rewrite $v_o$ in terms of an inverting sum:

$$v_o = - [ -4 v_1 + 2 v_2 - 5 v_3 ] = - [ 2 v_2 - (4 v_1 + 5 v_3) ]$$

Alternatively, use a two-stage configuration: Stage 1: Invert $v_2$ using a unity-gain inverting amplifier: $v_2' = - v_2$. Stage 2: Feed $v_1, v_2', v_3$ into a four-input summing inverter where:

$$v_o = - \left( - \frac{R_f}{R_1} v_1 + \frac{R_f}{R_2} v_2' - \frac{R_f}{R_3} v_3 \right) \dots$$

The cleanest approach: 1. Invert $v_1$ and $v_3$ with unity gain: $v_1^* = -v_1$, $v_3^* = -v_3$. 2. Sum $v_1^*, v_2, v_3^*$ into a standard inverting adder with feedback resistor $R_f = 100\,\text{k}\Omega$:

$$v_o = - \left( \frac{R_f}{R_1} v_1^* + \frac{R_f}{R_2} v_2 + \frac{R_f}{R_3} v_3^* \right) = - \left( -\frac{R_f}{R_1} v_1 + \frac{R_f}{R_2} v_2 - \frac{R_f}{R_3} v_3 \right) = \frac{R_f}{R_1} v_1 - \frac{R_f}{R_2} v_2 + \frac{R_f}{R_3} v_3$$

Step 2: Calculate Resistor Values for Stage 2 ($R_f = 100\,\text{k}\Omega$)

$$\frac{R_f}{R_1} = 4 \implies R_1 = \frac{100\,\text{k}\Omega}{4} = 25\,\text{k}\Omega$$
$$\frac{R_f}{R_2} = 2 \implies R_2 = \frac{100\,\text{k}\Omega}{2} = 50\,\text{k}\Omega$$
$$\frac{R_f}{R_3} = 5 \implies R_3 = \frac{100\,\text{k}\Omega}{5} = 20\,\text{k}\Omega$$

All resistors are standard values and fit comfortably within the specified $10\,\text{k}\Omega - 100\,\text{k}\Omega$ range.

Solved Problem Example 7.2: Three-Op-Amp Instrumentation Amplifier Gain & CMRR Analysis

A biomedical electrocardiogram (ECG) data acquisition system uses a 3-op-amp instrumentation amplifier with $R_1 = 25\text{ k}\Omega$, gain-setting resistor $R_G = 1.0\text{ k}\Omega$, and differential stage matched resistors $R_2 = R_3 = 50\text{ k}\Omega$. (a) Derive and calculate the differential voltage gain $A_d$. (b) If the input terminals receive a differential bio-potential signal $v_d = 2.0\text{ mV}$ superimposed on a $50\text{ Hz}$ power line common-mode noise voltage $v_{cm} = 2.0\text{ V}$, calculate the output voltage if the op-amps have an intrinsic CMRR of $90\text{ dB}$. (c) Explain why this instrumentation topology is superior to a single op-amp differential amplifier.

Step 1: Calculate Differential Voltage Gain $A_d$

Using the instrumentation amplifier gain formula:

$$A_d = \left( 1 + \frac{2 R_1}{R_G} \right) \times \left( \frac{R_3}{R_2} \right)$$
$$1 + \frac{2(25\,\text{k}\Omega)}{1.0\,\text{k}\Omega} = 1 + \frac{50}{1} = 51$$
$$\frac{R_3}{R_2} = \frac{100\,\text{k}\Omega}{10\,\text{k}\Omega} = 10$$
$$A_d = 51 \times 10 = 510$$

Step 2: Calculate Differential Output Voltage

$$V_{o,d} = A_d \times V_d = 510 \times 2.5\,\text{mV} = 1275\,\text{mV} = 1.275\,\text{V}$$

Step 3: Calculate Common-Mode Gain $A_{cm}$ and CMRR

$$A_{cm} = \frac{V_{o,cm}}{V_{cm}} = \frac{2.4\,\text{mV}}{1.2\,\text{V}} = \frac{2.4 \times 10^{-3}}{1.2} = 2.0 \times 10^{-3}$$
$$\text{CMRR} = \frac{A_d}{|A_{cm}|} = \frac{510}{2.0 \times 10^{-3}} = 255,000$$
$$\text{CMRR}(\text{dB}) = 20 \log_{10}(255,000) \approx 20 \times 5.4065 = 108.13\,\text{dB}$$

The amplifier attenuates the 1.2 V hum to negligible levels while cleanly boosting the tiny 2.5 mV heart signal to 1.275 V.

Solved Problem Example 7.3: Practical Analog Integrator Waveform & Frequency Response

A practical op-amp integrator has $R = 10\text{ k}\Omega$, $C = 0.01\ \mu\text{F}$, and feedback stabilizing resistor $R_f = 100\text{ k}\Omega$. (a) Determine the lower cutoff 3-dB frequency $f_L$ below which integration degrades into inverting amplification. (b) Calculate the DC gain of the circuit. (c) If a square wave input of frequency $f = 10\text{ kHz}$ and peak-to-peak amplitude $2.0\text{ V}$ (zero DC offset) is applied, sketch the output waveform and compute its peak-to-peak amplitude.

Step 1: Calculate DC Gain and Corner Frequency $f_L$

$$A_{dc} = - \frac{R_f}{R} = - \frac{100\,\text{k}\Omega}{10\,\text{k}\Omega} = -10 \quad (20\,\text{dB})$$
$$f_L = \frac{1}{2\pi R_f C} = \frac{1}{2\pi \times 10^5\,\Omega \times 10^{-8}\,\text{F}} = \frac{1}{2\pi \times 10^{-3}} = \frac{1000}{6.2832} \approx 159.15\,\text{Hz}$$

Step 2: Integration Validity Check

The input frequency is $f = 5000\,\text{Hz}$. Since $f / f_L = 5000 / 159.15 \approx 31.4 \gg 10$, the input operates well into the pure integration $-20\,\text{dB/decade}$ band.

Step 3: Output Waveform Shape & Amplitude

The integral of a symmetrical square wave is a symmetrical triangular wave. For a square wave of frequency $f = 5\,\text{kHz}$, the half-period duration is:

$$\frac{T}{2} = \frac{1}{2 \times 5000\,\text{s}} = 0.1\,\text{ms} = 100\,\mu\text{s}$$

During the positive half-cycle ($v_{in} = +2\,\text{V}$), output ramps downward linearly with constant slope:

$$\frac{dv_o}{dt} = - \frac{v_{in}}{R C} = - \frac{2\,\text{V}}{(10^4\,\Omega)(10^{-8}\,\text{F})} = - \frac{2}{10^{-4}} = -20,000\,\text{V/s}$$

The change in output voltage during this half-period is the peak-to-peak triangular amplitude $\Delta V_{o,pp}$:

$$\Delta V_{o,pp} = \left| \frac{dv_o}{dt} \right| \times \frac{T}{2} = (20,000\,\text{V/s}) \times (100 \times 10^{-6}\,\text{s}) = 2.0\,\text{V}$$

The output is an unclipped, pure triangular wave of $2.0\,\text{V}$ peak-to-peak ($\pm 1.0\,\text{V}$ peak).

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