Power Electronics: Thyristors, UJT & Phase Control

1. Physical Architecture and Operating Regimes

The Silicon Controlled Rectifier (SCR) is a four-layer, three-junction ($p_1-n_1-p_2-n_2$) unidirectional semiconductor switching device with three terminals: Anode (A), Cathode (K), and Gate (G). The outer layers are heavily doped $p_1$ (anode) and $n_2$ (cathode), while the inner $n_1$ and $p_2$ layers are moderately/lightly doped.

When an SCR is connected with an external anode-to-cathode voltage $V_{AK}$:

• Reverse Blocking State ($V_{AK} < 0$): Junctions $J_1$ and $J_3$ are reverse-biased, while $J_2$ is forward-biased. Only a minuscule reverse leakage current flows until the reverse breakdown voltage $V_{BR}$ is reached, at which point avalanche breakdown occurs.
• Forward Blocking State ($V_{AK} > 0$, $I_G = 0$): Outer junctions $J_1$ and $J_3$ are forward-biased, but central junction $J_2$ is reverse-biased, creating a wide depletion layer. The device supports high forward voltage with only a tiny forward leakage current flowing until the forward breakover voltage $V_{BO}$ is exceeded.
• Forward Conduction State ($V_{AK} > 0$, $I_G > I_{GT}$): Injection of a gate trigger pulse causes instantaneous regenerative switching (turn-on). Junction $J_2$ collapses, and the SCR drops into a low-impedance forward conduction state with a forward voltage drop of only $V_F \approx 1.0\text{ to }1.5\,\text{V}$.

2. Mathematical Derivation of Two-Transistor Regenerative Analogy

To mathematically understand regenerative latching, consider splitting the four-layer $p_1-n_1-p_2-n_2$ structure into two interconnected bipolar transistors: a PNP transistor $Q_1$ ($p_1-n_1-p_2$) and an NPN transistor $Q_2$ ($n_1-p_2-n_2$).

The collector of $Q_1$ feeds the base of $Q_2$, and the collector of $Q_2$ feeds the base of $Q_1$. Let $\alpha_1$ and $\alpha_2$ denote the common-base current gains of $Q_1$ and $Q_2$ respectively, and let $I_{CO1}, I_{CO2}$ be their reverse saturation currents.

Applying Kirchhoff's Current Law at the cathode: $I_K = I_A + I_G$. The total current crossing central junction $J_2$ is the sum of collector currents and reverse leakage:

Collecting terms in $I_A$:

Latching Condition: At very low current levels, transistor gains $\alpha_1$ and $\alpha_2$ are very small ($\ll 0.5$), so $(\alpha_1 + \alpha_2) \ll 1$, keeping $I_A$ negligible (off-state). However, when gate current $I_G$ is injected into the base of $Q_2$, $I_A$ increases, causing emitter currents to rise. Because transistor $\alpha$ increases nonlinearly with emitter current, the loop gain sum reaches unity:

Once $\alpha_1 + \alpha_2 = 1$, the internal regenerative loop feeds itself: $Q_1$ drives $Q_2$, which in turn drives $Q_1$. At this stage, the external gate signal $I_G$ loses control and can be safely removed; the device remains latched in the ON state.

3. Latching Current ($I_L$) vs. Holding Current ($I_H$)

• Latching Current ($I_L$): The minimum anode current that must be attained immediately after gate triggering for the SCR to sustain conduction when the gate trigger pulse is terminated. If $I_A < I_L$ when $I_G$ ceases, the SCR falls back into the forward blocking state.
• Holding Current ($I_H$): The minimum anode current below which the SCR automatically turns OFF (re-enters the forward blocking mode) during commutation. If an external circuit reduces $I_A$ below $I_H$, the regenerative loop collapses.
• Crucial Relationship: For all thyristors, $I_L > I_H$, typically $I_L \approx 2\text{ to }3 \times I_H$.

1. Firing Angle $\alpha$ and Conduction Angle $\gamma$

In AC power circuits, the point on the sinusoidal voltage waveform at which the SCR is triggered into conduction is quantified by the firing angle (or delay angle) $\alpha$ measured in electrical degrees or radians from the zero-crossing of the positive half-cycle ($0 \le \alpha \le \pi$).

The conduction angle $\gamma$ represents the duration over which the SCR conducts before natural line commutation turns it off:

2. Half-Wave Phase-Controlled Rectifier with Resistive Load

Consider an AC source $v_s(t) = V_m \sin(\omega t)$ connected to an SCR in series with a resistive load $R$. During the negative half-cycle ($\pi \le \omega t \le 2\pi$), the SCR is reverse-biased and $v_o(t) = 0$. During the positive half-cycle, conduction begins only when triggered at $\omega t = \alpha$ and extinguishes naturally at $\omega t = \pi$.

The average (DC) load voltage is derived via definite integration:

The RMS load voltage is calculated by evaluating the root-mean-square integral:

3. Full-Wave Mid-Point & Bridge Phase-Controlled Rectifier

For a full-wave controlled bridge rectifier where SCR pairs are fired symmetrically at $\alpha$ and $\pi + \alpha$:

When $\alpha = 0$, $V_{dc} = \frac{2V_m}{\pi}$, which corresponds exactly to an uncontrolled full-wave diode rectifier. By modulating $\alpha$ continuously from $0$ to $\pi$, $V_{dc}$ smoothly varies from $\frac{2V_m}{\pi}$ down to $0\,\text{V}$, providing continuous DC motor speed and heating control.

1. Architecture and Equivalent Circuit of UJT

The Unijunction Transistor (UJT) is a three-terminal single-junction device consisting of a lightly doped $N$-type silicon bar with ohmic contacts at both ends, denoted as Base-1 ($B_1$) and Base-2 ($B_2$). Near $B_2$, a heavily doped $P$-type emitter region is alloyed, forming a single $P-N$ junction with the bar.

The total resistance of the silicon bar between $B_1$ and $B_2$ when the emitter is open-circuited is the interbase resistance $R_{BB}$:

The internal voltage division between Base 1 and Base 2 defines the fundamental device parameter, the Intrinsic Standoff Ratio $\eta$:

2. Dynamic Conduction & Negative Resistance Characteristic

When an interbase bias $V_{BB}$ is applied with $B_2$ positive relative to $B_1$, the potential at the internal junction point $A$ inside the silicon bar is $V_A = \eta V_{BB}$.

If emitter voltage $V_E < V_A + V_D$ (where $V_D \approx 0.6\,\text{V}$ is the silicon diode forward barrier drop), the emitter junction is reverse-biased, permitting only a tiny reverse leakage current $I_{EO}$ to flow (Cutoff Region).

When $V_E$ reaches the Peak-Point Voltage $V_P$:

The emitter junction becomes forward-biased, injecting a burst of holes into the $N$-type channel between the emitter and $B_1$. This massive carrier injection drastically lowers the resistance $R_{B1}$ via conductivity modulation. As $I_E$ increases, $V_E$ rapidly plummets, establishing a dynamic Negative Differential Resistance region ($dV_E/dI_E < 0$) until reaching the Valley Point $(V_V, I_V)$, beyond which the device enters saturation.

3. UJT Relaxation Oscillator Circuit & Derivation of Period

In a relaxation oscillator, a timing resistor $R$ charges an external capacitor $C$ from $V_{BB}$. As $C$ charges, capacitor voltage rises exponentially:

When $v_C(t)$ reaches the peak point $V_P \approx \eta V_{BB}$ (neglecting small $V_D$ and assuming discharge to $V_V \approx 0$):

Taking the natural logarithm of both sides yields the oscillation period $T$ and frequency $f$:

When the capacitor discharges rapidly through the low resistance of $R_{B1}$ and an external resistor $R_1$, a sharp, high-energy positive voltage pulse is developed across $R_1$, perfectly matched for reliably triggering SCR and Triac gates.

1. Diac (Diode AC Switch): Symmetrical Bi-directional Trigger

A Diac is a three-layer, two-terminal ($A_1$ and $A_2$) bidirectional semiconductor diode. It does not have a control gate. The device remains in forward or reverse blocking mode until the applied voltage across its terminals reaches the symmetrical breakover voltage $V_{BO}$ (typically $\pm 30\text{ to }35\,\text{V}$).

Once $|V| \ge V_{BO}$, the Diac undergoes negative-resistance breakdown, dropping terminal voltage suddenly to $\sim 20\,\text{V}$ and discharging a sharp spike of current in either positive or negative polarity. This makes Diacs the primary trigger element for driving Triac gates symmetrically on both alternating half-cycles.

2. Triac (Triode AC Switch): Architecture and Quadrant Modes

A Triac is functionally equivalent to two inverse-parallel (back-to-back) SCRs integrated monolithically on a single silicon chip with a single common gate terminal. The main power terminals are designated Main Terminal 1 (MT1) and Main Terminal 2 (MT2), referenced to MT1.

A Triac can be triggered into conduction by either a positive or negative gate pulse for either polarity of terminal voltage $V_{MT2-MT1}$, operating across four quadrants:

• Mode I+ ($MT2+, G+$): Most sensitive mode. Both MT2 and Gate are positive with respect to MT1. Normal transistor junction action.
• Mode I- ($MT2+, G-$): MT2 positive, Gate negative with respect to MT1. Gate junction junction injection initiates turn-on.
• Mode III+ ($MT2-, G+$): MT2 negative, Gate positive with respect to MT1. Least sensitive mode requiring highest gate trigger current $I_{GT}$. Often avoided in symmetrical trigger circuits.
• Mode III- ($MT2-, G-$): Highly sensitive mode. MT2 negative, Gate negative. Remote gate injection triggering.

3. Full-Wave AC Phase Control (Light Dimmer Circuit)

In a standard phase-controlled light dimmer or AC fan motor speed controller:

• A potentiometer $R_v$ and fixed resistor $R_1$ charge capacitor $C$ from the AC mains line.
• The voltage across $C$ lags behind the line voltage by phase angle $\theta = \arctan(\omega R_{total} C)$.
• When capacitor voltage $|v_C(t)|$ reaches the Diac breakdown voltage $V_{BO} \approx 32\,\text{V}$, the Diac breaks down and rapidly dumps capacitor charge into the Triac gate.
• The Triac fires into full conduction, applying the remaining portion of the mains half-cycle to the lamp or motor load.
• At the end of the half-cycle, when AC load current crosses zero, the Triac commutates off naturally until the Diac fires in the opposite polarity during the subsequent half-cycle.

Adjusting $R_v$ varies the firing delay angle $\alpha$ continuously from $\approx 15^\circ$ to $\approx 165^\circ$, smoothly controlling the RMS power delivered to the load from $\approx 98\%$ down to $0\%$.