Transistor Amplifiers: Small-Signal, Multistage & Power Stages

1. Two-Port Network Formalism and Hybrid h-Parameters

For small alternating signals superimposed on DC quiescent operating points, a bipolar junction transistor in Common Emitter (CE) configuration is modeled linearly as a two-port network relating input voltage $v_b$, input current $i_b$, output current $i_c$, and output voltage $v_c$:

The four parameters are precisely defined under AC short-circuit and open-circuit conditions:

• $h_{ie} = \left.\frac{v_b}{i_b}\right|_{v_c = 0}$ : Short-circuit input impedance $(\Omega)$
• $h_{re} = \left.\frac{v_b}{v_c}\right|_{i_b = 0}$ : Open-circuit reverse voltage ratio (dimensionless, typically $\sim 10^{-4}$)
• $h_{fe} = \left.\frac{i_c}{i_b}\right|_{v_c = 0}$ : Short-circuit forward current transfer ratio / AC current gain $(\beta_{ac})$
• $h_{oe} = \left.\frac{i_c}{v_c}\right|_{i_b = 0}$ : Open-circuit output admittance $(\text{S} = \Omega^{-1}$, typically $\sim 20\,\mu\text{S}$)

2. Simplified CE Hybrid Model & Gain Derivations

In standard practical audio and RF amplifier design, $h_{re} \approx 0$ (reverse feedback negligible) and $h_{oe} R_L \ll 0.1$ (output conductances much smaller than load conductance). The circuit simplifies to an input resistor $h_{ie}$ and a dependent current source $h_{fe} i_b$.

With an effective AC collector load $R_L' = R_C \parallel R_L$:

Hence, the Voltage Gain $A_v$ is:

The negative sign reflects the fundamental $180^\circ$ phase inversion between input base signal and output collector signal in a Common Emitter amplifier.

The Current Gain $A_i$, Input Impedance $Z_{in}$, and Output Impedance $Z_{out}$ are:

3. Frequency Response and Cutoff Frequencies

The frequency response curve of a CE amplifier exhibits three distinct regimes:

• Low-Frequency Range ($f < f_L$): The reactances of coupling capacitors $C_1, C_2$ and emitter bypass capacitor $C_E$ ($X_C = 1/(2\pi f C)$) grow large. This introduces voltage division and degenerative negative feedback across $R_E$, reducing voltage gain at a slope of $+20\,\text{dB/decade}$ per dominant pole.
• Midband Range ($f_L \le f \le f_H$): Coupling/bypass capacitors act as virtual short circuits ($X_C \approx 0$), while internal parasitic transistor capacitances act as virtual open circuits. The gain remains flat at maximum midband gain $A_{vm}$.
• High-Frequency Range ($f > f_H$): The internal depletion and diffusion capacitances (base-emitter capacitance $C_\pi$ and base-collector Miller capacitance $C_\mu$) introduce shunting paths to ground, rolling off gain at $-20\,\text{dB/decade}$.

The Bandwidth ($BW$) is defined between the half-power ($-3\,\text{dB}$) points:

1. Cascading Amplifiers & Decibel Gain Formalism

A single transistor stage often cannot simultaneously provide adequate voltage gain, current drive, and impedance matching. Multiple amplifier stages are therefore cascaded in series, where the output of stage $n$ serves as the input to stage $n+1$.

The overall voltage gain is the multiplicative product of individual loaded gains:

Expressed logarithmically in Decibels (dB):

Decibels convert complicated cascading products into simple additions.

2. Comparative Analysis of Coupling Schemes

3. Loading Effect in RC-Coupled Cascades

When stage 1 is coupled to stage 2 through capacitor $C_c$, the effective AC load seen by collector 1 is not simply $R_{C1}$, but the parallel combination of $R_{C1}$ and the input impedance of stage 2:

Because $R_{L1}' < R_{C1}$, the loaded gain $A_{v1}$ is significantly smaller than the open-circuit gain of an isolated stage. Neglecting this loading effect produces massive design errors.

1. Large-Signal Operation & Conduction Angle Classifications

Unlike small-signal voltage amplifiers that handle millivolt signals, Power Amplifiers (large-signal amplifiers) deliver significant power (watts to kilowatts) into low-impedance loads (speakers, antennas) with high efficiency while keeping device dissipation within thermal tolerances ($T_j < T_{j,max}$).

Amplifier classes are categorized strictly by the conduction angle $\theta_c$ of the collector current during one complete sinusoidal input cycle ($360^\circ$):

• Class A ($\theta_c = 360^\circ$ or $2\pi$ radians): The transistor conducts continuously for the entire input cycle. The Q-point is biased in the center of the active linear region. Distortions are minimal, but static DC power is continually wasted even with zero signal.
• Class B ($\theta_c = 180^\circ$ or $\pi$ radians): The transistor is biased exactly at cutoff ($I_{CQ} = 0$). Conduction occurs for exactly one half-cycle ($180^\circ$). Zero static DC power at idle.
• Class AB ($180^\circ < \theta_c < 360^\circ$): Biased slightly above cutoff with a small quiescent current ($I_{CQ} > 0$). Conduction occurs for slightly more than half a cycle, eliminating Class B crossover distortion.
• Class C ($\theta_c < 180^\circ$): Biased well beyond cutoff. Conduction occurs in brief pulses ($80^\circ - 120^\circ$). High harmonic distortion; used exclusively with tuned resonant LC tanks in high-efficiency RF transmitters.

2. Mathematical Derivation of Maximum Collector Efficiency

Collector Efficiency $\eta$ is defined as the ratio of average AC output power delivered to the load to the average DC power drawn from the power supply:

(a) Series-Fed Class A Amplifier

For a series-fed Class A amplifier with supply $V_{CC}$ and collector resistor $R_C$:

Under maximum unclipped sinusoidal swing, $V_m = V_{CC}/2$ and $I_m = I_{CQ} = V_{CC}/(2 R_C)$:

For a transformer-coupled Class A amplifier, the DC drop across the primary is near zero, allowing peak-to-peak voltage swing up to $2 V_{CC}$, doubling the theoretical limit to $\eta_{max} = 50\%$.

(b) Push-Pull Class B Amplifier

In a complementary-symmetry push-pull Class B configuration operating from a supply $V_{CC}$ (or dual $\pm V_{CC}$):

For peak load voltage $V_m$ across load $R_L$, peak collector current is $I_m = V_m / R_L$. The average current drawn from the DC supply during half-wave pulses by each rail is $I_{dc} = \frac{2}{\pi} I_m$. Thus:

The AC power delivered to the load is:

Collector efficiency as a function of output swing is:

Under maximum theoretical output voltage swing where $V_m = V_{CC}$:

1. Push-Pull Operation & Harmonic Distortion Cancellation

A push-pull amplifier utilizes two matched transistors ($Q_1$ and $Q_2$) operating in anti-phase: $Q_1$ conducts during the positive half-cycle of the input signal, pushing current into the load, while $Q_2$ conducts during the negative half-cycle, pulling current from the load.

Mathematically, expanding the nonlinear collector current transfer characteristics in a Taylor series:

In a balanced push-pull output transformer, net load current is proportional to the difference $i_{c1} - i_{c2}$:

Crucial Result: All even-order harmonic distortion terms ($a_2 v_{in}^2, a_4 v_{in}^4$) completely cancel out! Furthermore, DC core saturation in output transformers is eliminated because quiescent currents produce opposing magnetic fluxes.

2. Crossover Distortion in Pure Class B

In a pure Class B push-pull stage, transistors are biased at $V_{BE} = 0$. However, real silicon bipolar transistors require a threshold forward voltage $V_{BE} \approx 0.6\text{ to }0.7\,\text{V}$ before base-emitter conduction begins.

Consequently, whenever the input signal passes through the zero-crossing within the deadband $-0.7\,\text{V} < v_{in} < +0.7\,\text{V}$, neither transistor conducts ($i_{c1} = i_{c2} = 0$). The output waveform flattens to zero near every crossing, generating severe high-order harmonic distortion known as Crossover Distortion.

3. Class AB Biasing and Diode Thermal Tracking

To eliminate crossover distortion, the transistors are biased into Class AB by applying a slight forward bias ($V_{bias} \approx 2 V_D \approx 1.4\,\text{V}$) across the base terminals using two series silicon diodes ($D_1, D_2$) or an active $V_{BE}$-multiplier circuit.

This maintains both transistors barely conducting at an idle quiescent current $I_{CQ} \approx 10\text{ to }50\,\text{mA}$. When the input swings through zero, the conduction smoothly transfers from $Q_1$ to $Q_2$ with zero deadband. Mounting the biasing diodes on the same physical heatsink as the power output transistors ensures thermal tracking: as junction temperature rises, diode voltage drops at $-2\,\text{mV}/^\circ\text{C}$, matching the transistor $V_{BE}$ drop and preventing thermal runaway.